NCP1015
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10
Plugging Equation 7 and Equation 8 into Equation 6 leads
to <V
ds(t)
> = V
in
and thus:
P
DSS
+ V
in
@ ICC1
(eq. 9)
The worse case occurs at high line, when V
in
equals
370 Vdc. With ICC1 = 1.2 mA (65 kHz version), we can
expect a DSS dissipation around 440 mW. If you select a
higher switching frequency version, the ICC1 increases and
it is likely that the DSS consumption exceeds 500 mW. In
that case, we recommend adding an auxiliary winding in
order to offer more dissipation room to the power MOSFET.
Please read application note AND8125/D “Evaluating the
power capability of the NCP101X members” to help
selecting the right part / configuration for your application.
Lowering the Standby Power with an Auxiliary
Winding
The DSS operation can bother the designer when a) its
dissipation is too high b) extremely low standby power is a
must. In both cases, one can connect an auxiliary winding to
disable the selfsupply. The current source then ensures the
startup sequence only and stays in the off state as long as
V
CC
does not drop below V
CC(on)
or 7.5 V. Figure 17 shows
that the insertion of a resistor (R
limit
) between the auxiliary
dc level and the V
CC
pin is mandatory a) not to damage the
internal 8.7 V zener diode during an overshoot for instance
(absolute maximum current is 15 mA) b) to implement the
failsafe optocoupler protection as offered by the active
clamp. Please note that there cannot be bad interaction
between the clamping voltage of the internal zener and
V
CC(off)
since this clamping voltage is actually built on top
of V
CC(off)
with a fixed amount of offset (200 mV typical).
Selfsupplying controllers in extremely low standby
applications often puzzles the designer. Actually, if a SMPS
operated at nominal load can deliver an auxiliary voltage of
an arbitrary 16 V (V
nom
), this voltage can drop to below
10 V (V
stby
) when entering standby. This is because the
recurrence of the switching pulses expands so much that the
low frequency refueling rate of the V
CC
capacitor is not
enough to keep a proper auxiliary voltage. Figure 18 shows
a typical scope shot of a SMPS entering deep standby
(output unloaded). So care must be taken when calculating
R
limit
1) to not excess the maximum pin current in normal
operation but 2) not to drop too much voltage over R
limit
when entering standby. Otherwise the DSS could reactivate
and the standby performance would degrade. We are thus
able to bound R
limit
between two equations:
V
nom
* V
clamp
I
trip
v R
lim
v
V
stby
* V
CC(on)
ICC1
(eq. 10)
Where:
V
nom
is the auxiliary voltage at nominal load
V
stdby
is the auxiliary voltage when standby is entered
I
trip
is the current corresponding to the nominal operation.
It thus must be selected to avoid false tripping in overshoot
conditions.
ICC1 is the controller consumption. This number slightly
decreases compared to ICC1 from the spec since the part in
standby does almost not switch.
V
CC(on)
is the level above which V
aux
must be maintained
to keep the DSS in the OFF mode. It is good to shoot around
8 V in order to offer an adequate design margin, e.g. to not
reactivate the startup source (which is not a problem in
itself if low standby power does not matter)
Since R
limit
shall not bother the controller in standby, e.g.
keep V
aux
to around 8 V (as selected above), we purposely
select a V
nom
well above this value. As explained before,
experience shows that a 40% decrease can be seen on
auxiliary windings from nominal operation down to standby
mode. Let’s select a nominal auxiliary winding of 20 V to
offer sufficient margin regarding 8 V when in standby (R
limit
also drops voltage in standby). Plugging the values in
Equation 10 gives the limits within which R
limit
shall be
selected:
20 * 8.7
6.3 m
v R
limit
v
12 * 8
1.1 m
(eq. 11)
that is to say: 1.8 kW < R
limit
< 3.6 kW.
If we are designing a power supply delivering 12 V, then
the ratio auxiliary/power must be: 12 / 20 = 0.6. The I
CC
current has to not exceed 6.4 mA. This will occur when V
aux
growsup to: 8.7 V + 1.8 k x (6.4 m + 1.1 m) = 22.2 V for
the first boundary or 8.7 V + 3.6 k x (6.4 m +1.1 m) = 35.7 V
for second boundary. On the power output, it will
respectively give 22.6 x 0.6 = 13.3 V and 35.7 x 0.6 = 21.4 V.
As one can see, tweaking the R
limit
value will allow the
selection of a given overvoltage output level. Theoretically
predicting the auxiliary drop from nominal to standby is an
almost impossible exercise since many parameters are
involved, including the converter time constants. Fine
tuning of R
limit
thus requires a few iterations and
experiments on a breadboard to check V
aux
variations but
also output voltage excursion in fault. Once properly
adjusted, the failsafe protection will preclude any lethal
voltage runaways in case a problem would occur in the
feedback loop.
NCP1015
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11
Figure 17. A Detailed View of the NCP1015 with Properly Connected Auxiliary Winding
Startup Source
Drain
+
-
+
V
CC(off)
= 8.5 V
V
CC(on)
= 7.5 V
+
V
CC
Rlimit
+ +
CVCC CAux
Laux
Ground
+
D1
Figure 18. The Burst Frequency becomes So Low that it is Difficult to
Keep an Adequate Level on the Auxiliary V
CC
u30 ms
Lowering the Standby Power with Skipcycle
Skip cycle offers an efficient way to reduce the standby
power by skipping unwanted cycles at light loads. However,
the recurrent frequency in skip often enters the audible range
and a high peak current obviously generates acoustic noise
in the transformer. The noise takes its origins in the
resonance of the transformer mechanical structure which is
excited by the skipping pulses. A possible solution,
successfully implemented in the NCP1200 series, also
authorizes skip cycle but only when the power demand as
dropped below a given level. At this time, the peak current
is reduced and no noise can be heard. Figure 19 shows the
peak current evolution of the NCP1015 entering standby:
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12
Figure 19. Low Peak Current SkipCycle Guarantees NoiseFree Operation
100%
Peak current
at nominal power
25%
Skipcycle
current limit
Full power operation involves the nominal switching
frequency and thus avoids any noise when running.
Experiments carried on a 5 W universal mains board
unveiled a standby power of 300 mW @ 230 Vac with the
DSS activated and dropped to less than 100 mW when an
auxiliary winding is connected.
Frequency Jittering for Improved EMI Signature
By sweeping the switching frequency around its nominal
value, it spreads the energy content on adjacent frequencies
rather than keeping it centered in one single ray. This offers
the benefit to artificially reduce the measurement noise on
a standard EMI receiver and pass the tests more easily. The
EMI sweep is implemented by routing the V
CC
ripple
(induced by the DSS activity) to the internal oscillator. As a
result, the switching frequency moves up and down to the
DSS rhythm. Typical deviation is
±4% of the nominal
frequency. With a 1 V peaktopeak ripple, the frequency
will equal 65 kHz in the middle of the ripple and will
increase as V
CC
rises or decrease as V
CC
ramps down.
Figure 20 shows the behavior we have adopted:
Figure 20. The V
CC
Ripple Causes the Frequency Jittering on the Internal Oscillator Sawtooth
(65 kHz version)
V
CC
Ripple
VCC
OFF
67.6 kHz
65 kHz
62.4 kHz
VCC
ON
Internal Sawtooth

NCP1015ST65T3G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Switching Controllers MONOLTHC SWTCHR SMPS
Lifecycle:
New from this manufacturer.
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