NCP1015
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13
SoftStart
The NCP1015 features an internal 1 ms softstart
activated during the power on sequence (P
ON
). As soon as
V
CC
reaches V
CC(off)
, the peak current is gradually
increased from nearly zero up to the maximum internal
clamping level (e.g. 350 mA). This situation lasts 1 ms and
further to that time period, the peak current limit is blocked
to the maximum until the supply enters regulation. The
softstart is also activated during the over current burst
(OCP) sequence. Every restart attempt is followed by a
softstart activation. Generally speaking, the softstart will
be activated when V
CC
ramps up either from zero (fresh
poweron sequence) or 4.5 V, the latchoff voltage
occurring during OCP. Figure 21 shows the softstart
behavior. The time scales are purposely shifted to offer a
better zoom portion.
Figure 21. SoftStart is Activated During a Startup Sequence or an OCP Condition
0 V (Fresh PON)
or
4.7 V (Overload)
V
CC
8.5 V
Current
Sense
Max Ip
1.0 ms
Nonlatching Shutdown
In some cases, it might be desirable to shut off the part
temporarily and authorize its restart once the default has
disappeared. This option can easily be accomplished
through a single NPN bipolar transistor wired between FB
and ground. By pulling FB below the internal skip level
(V
skip
), the output pulses are disabled. As soon as FB is
relaxed, the IC resumes its operation. Figure 22 shows the
application example:
Figure 22. A Nonlatching Shutdown where Pulses are Stopped as long as the NPN is Biased
ON/OFF
27
3
45
18
Transformer
+
CV
CC
Full Latching Shutdown
Other applications require a full latching shutdown, e.g.
when an abnormal situation is detected (over temp or
overvoltage). This feature can easily be implemented
through two external transistors wired as a discrete SCR.
When the OVP level exceeds the zener breakdown voltage,
the NPN biases the PNP and fires the equivalent SCR,
permanently bringing down the FB pin. The switching
pulses are disabled until the user unplugs the power supply.
NCP1015
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14
Figure 23. Two Bipolar Transistors Ensures a Total Latchoff of the SMPS in Presence of an OVP
27
3
45
18
Transformer
+
CV
CC
BAT54
10 k
10 k
OVP
Rhold
12 k
0.1 mF
R
hold
ensures that the SCR stays on when fired. The bias
current flowing through R
hold
should be small enough to let
the V
CC
ramp up (8.5 V) and down (7.5 V) when the SCR
is fired. The NPN base can also receive a signal from a
temperature sensor. Typical bipolar can be MMBT2222 and
MMBT2907 for the discrete latch. The NST3946 features
two bipolar NPN + PNP in the same package and could also
be used.
Power Dissipation and Heatsinking
The power dissipation of NCP1015 consists of the
dissipation DSS currentsource (when active) and the
dissipation of MOSFET. Thus P
tot
= P
DSS
+ P
MOSFET
.
When the PDIP7 package is surrounded by copper, it
becomes possible to drop its thermal resistance
junctiontoambient, R
q
JA
down to 75°C/W and thus
dissipate more power. The maximum power the device can
thus evacuate is:
P
max
+
T
J(max)
* T
AMB(max)
R
qJA
(eq. 12)
which gives around 1 W for an ambient of 50°C. The losses
inherent to the MOSFET R
DS(on)
can be evaluated using the
following formula:
P
mos
+
1
3
@ I
p
2
@ D @ R
DS(on)
(eq. 13)
where I
p
is the worse case peak current (at the lowest line
input), D is the converter operating dutycycle and R
DS(on)
the MOSFET resistance for T
J
= 100°C. This formula is only
valid for Discontinuous Conduction Mode (DCM)
operation where the turnon losses are null (the primary
current is zero when you restart the MOSFET). Figure 24
gives a possible layout to help dropping the thermal
resistance. When measured on a 35 mm (1 oz.) copper
thickness PCB, we obtained a thermal resistance of 75°C/W:
Figure 24. A Possible PCB Arrangement to Reduce the Thermal Resistance JunctiontoAmbient
Clamping Elements
DC
To Secondary Diode
Design Procedure
The design of a SMPS around a monolithic device does
not differ from that of a standard circuit using a controller
and a MOSFET. However, one needs to be aware of certain
characteristics specific of monolithic devices:
1. In any case, the lateral MOSFET bodydiode shall
never be forward biased, either during startup
(because of a large leakage inductance) or in
normal operation as shown by Figure 25.
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15
Figure 25. The DrainSource Wave Shall Always be Positive . . .
1.004M 1.011M 1.018M 1.025M 1.032M
50.0
50.0
150
250
350
> 0 !!
As a result, the Flyback voltage which is reflected on
the drain at the switch opening cannot be larger than
the input voltage. When selecting components, you
thus must adopt a turn ratio which adheres to the
following equation:
N @ (V
out
) V
f
) t V
IN(min)
(eq. 14)
For instance, if you operate from a 120 V dc rail and
you deliver 12 V, we can select a reflected voltage of
100 VDC maximum: 120 100 > 0. Therefore, the
turn ratio Np : Ns must be smaller than 100 / (12 +
1) = 7.7 or Np : Ns < 7.7. We will see later on how
it affects the calculation.
2. Currentmode architecture is, by definition,
sensitive to subharmonic oscillations.
Subharmonic oscillations only occur when the
SMPS is operating in Continuous Conduction
Mode (CCM) together with a dutycycle greater
than 50%. As a result, we recommend operating
the device in DCM only, whatever dutycycle it
implies (max. = 65%).
3. Lateral Mosfets have a poorly doped bodydiode
which naturally limits their ability to sustain the
avalanche. A traditional RCD clamping network
shall thus be installed to protect the MOSFET. In
some low power applications, a simple capacitor
can also be used since:
V
DRAIN(max)
+ V
in
) N @ (V
out
) V
f
) ) I
p
@
L
f
C
tot
Ǹ
(eq. 15)
where L
f
is the leakage inductance, C
tot
the total
capacitance at the drain node (which is increased by
the capacitor you will wire between drain and
source), N the Np : Ns turn ratio, V
out
the output
voltage, V
f
the secondary diode forward drop and
finally, I
p
the maximum peak current. Worse case
occurs when the SMPS is very close to regulation,
e.g. the V
out
target is almost reached and I
p
is still
pushed to the maximum.
Taking into account all previous remarks, it becomes
possible to calculate the maximum power that can be
transferred at low line:
When the switch closes, V
in
is applied across the primary
inductance L
p
until the current reaches the level imposed by
the feedback loop. The duration of this event is called the ON
time and can be defined by:
t
on
+
L
p
@ I
p
V
in
(eq. 16)
At the switch opening, the primary energy is transferred
to the secondary and the flyback voltage appears across L
p
,
reseting the transformer core with a slope of:
N @ (V
out
) V
f
)
L
p
@ t
off
the t
off
time is thus:
t
off
+
L
p
@ I
p
N @ (V
out
) V
f
)
(eq. 17)
If one wants to keep DCM only, but still need to pass the
maximum power, we will not allow a deadtime after the
core is reset, but rather immediately restart. The switching
time t
sw
can be expressed by:
t
sw
+ t
off
) t
on
+ L
p
@ I
p
@
ǒ
1
V
in
)
1
N @ (V
out
) V
f
)
Ǔ
(eq. 18)
The Flyback transfer formula dictates that:
P
out
h
+
1
2
@ L
p
@ I
p
2
@ f
sw
(eq. 19)
which, by extracting I
p
and plugging into Equation 19 leads to:
t
sw
+ L
p
2 @ P
out
h @ f
sw
@ L
p
Ǹ
@
ǒ
1
V
in
)
1
N @ (V
out
) V
f
)
Ǔ
(eq. 20)
Extracting L
p
from Equation 20 gives:

NCP1015ST65T3G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Switching Controllers MONOLTHC SWTCHR SMPS
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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