4K x 16/18 and 8K x 16/18
Dual-Port Static RAM with SEM, INT, BUSY
CY7C024E, CY7C0241E
CY7C025E, CY7C0251E
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 001-62932 Rev. *A Revised October 28, 2010
Features
■ True dual-ported memory cells that allow simultaneous reads
of the same memory location
■ 4K ×16 organization (CY7C024E)
■ 4K × 18 organization (CY7C0241E)
■ 8K × 16 organization (CY7C025E)
■ 8K × 18 organization (CY7C0251E)
■ 0.35-µ complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■ High-speed access: 15 ns
■ Low operating power: I
CC
= 180 mA (typ), I
SB3
= 0.05 mA (typ)
■ Fully asynchronous operation
■ Automatic power-down
■ Expandable data bus to 32/36 bits or more using master/slave
chip select when using more than one device
■ On-chip arbitration logic
■ Semaphores included to permit software handshaking
between ports
■ INT flag for port-to-port communication
■ Separate upper-byte and lower-byte control
■ Pin select for master or slave
■ Available in Pb-free 100-pin thin quad flatpack (TQFP) package
Functional Description
The CY7C024E/CY7C0241E and CY7C025E/CY7C0251E are
low-power CMOS 4K × 16/18 and 8K × 16/18 dual-port static
RAMs. Various arbitration schemes are included on the
CY7C024E/CY7C0241E and CY7C025E/CY7C0251E to handle
situations when multiple processors access the same piece of
data. Two ports are provided, permitting independent,
asynchronous access for reads and writes to any location in
memory. The CY7C024E/CY7C0241E and
CY7C025E/CY7C0251E can be used as standalone 16 or 18-bit
dual-port static RAMs or multiple devices can be combined to
function as a 32-/36-bit or wider master/ slave dual-port static
RAM. An M/S
pin is provided for implementing 32-/36-bit or wider
memory applications without the need for separate master and
slave devices or additional discrete logic. Application areas
include interprocessor/multiprocessor designs, communications
status buffering, and dual-port video/graphics memory.
Each port has independent control pins: Chip Enable (CE
), Read
or Write Enable (R/W
), and Output Enable (OE). Two flags are
provided on each port (BUSY
and INT). BUSY signals that the
port is trying to access the same location currently being
accessed by the other port. The Interrupt Flag (INT) permits
communication between ports or systems by means of a mail
box. The semaphores are used to pass a flag, or token, from one
port to the other to indicate that a shared resource is in use. The
semaphore logic is comprised of eight shared latches. Only one
side can control the latch (semaphore) at any time. Control of a
semaphore indicates that a shared resource is in use. An
automatic power-down feature is controlled independently on
each port by a CE
pin.
The CY7C024E/CY7C0241E and CY7C025E/CY7C0251E are
available in 100-pin Pb-free TQFP.
Selection Guide
Parameter –15 –25 –55
Maximum access time (ns) 15 25 55
Typical operating current (mA) 190 170 150
Typical standby current for I
SB1
(mA) 50 40 20
