CY62148ESL MoBL
®
4-Mbit (512 K × 8) Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 001-50045 Rev. *J Revised May 28, 2015
4-Mbit (512 K × 8) Static RAM
Features
■ Higher speed up to 55 ns
■ Wide voltage range: 2.2 V to 3.6 V
and 4.5 V to 5.5 V
■ Ultra low standby power
❐ Typical standby current: 1 µA
❐ Maximum standby current: 7 µA
■ Ultra low active power
❐ Typical active current: 2 mA at f = 1 MHz
■ Easy memory expansion with CE and OE features
■ Automatic power-down when deselected
■ Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■ Available in Pb-free 32-pin shrunk thin small outline package
(STSOP) package
Functional Description
The CY62148ESL is a high performance CMOS static RAM
organized as 512 K words by 8-bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL
) in portable
applications. The device also has an automatic power-down
feature that significantly reduces power consumption. Placing
the device in standby mode reduces power consumption by
more than 99 percent when deselected (CE
HIGH). The eight
input and output pins (I/O
0
through I/O
7
) are placed in a high
impedance state when the device is deselected (CE
HIGH), the
outputs are disabled (OE
HIGH), or during a write operation (CE
LOW and WE LOW).
To write to the device, take Chip Enable (CE) and Write Enable
(WE
) inputs LOW. Data on the eight I/O pins (I/O
0
through I/O
7
)
is then written into the location specified on the address pins (A
0
through A
18
).
To read from the device, take Chip Enable (CE
) and Output
Enable (OE
) LOW while forcing Write Enable (WE) HIGH. Under
these conditions, the contents of the memory location specified
by the address pins appear on the I/O pins.
The CY62148ESL device is suitable for interfacing with
processors that have TTL I/P levels. It is not suitable for
processors that require CMOS I/P levels. Please see Electrical
Characteristics on page 4 for more details and suggested
alternatives.
For a complete list of related resources, click here.
A
0
IO
0
IO
7
IO
1
IO
2
IO
3
IO
4
IO
5
IO
6
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
SENSE AMPS
POWER
DOWN
CE
WE
OE
A
13
A
14
A
15
A
16
A
17
ROW DECODER
COLUMN DECODER
512K x 8
ARRAY
INPUT BUFFER
A
10
A
11
A
12
A
18
Logic Block Diagram
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
