Document Number: 001-50045 Rev. *J Page 7 of 16
Switching Characteristics
Over the operating range
Parameter
[14, 15]
Description
55 ns (Industrial /
Automotive-A)
Unit
Min Max
Read Cycle
t
RC
Read cycle time 55 – ns
t
AA
Address to data valid – 55 ns
t
OHA
Data hold from address change 10 – ns
t
ACE
CE LOW to data valid – 55 ns
t
DOE
OE LOW to data valid – 25 ns
t
LZOE
OE LOW to low Z
[16]
5 – ns
t
HZOE
OE HIGH to high Z
[16, 17]
– 20 ns
t
LZCE
CE LOW to low Z
[16]
10 – ns
t
HZCE
CE HIGH to high Z
[16, 17]
– 20 ns
t
PU
CE LOW to power-up 0 – ns
t
PD
CE HIGH to power-up – 55 ns
Write Cycle
[18, 19]
t
WC
Write cycle time 55 – ns
t
SCE
CE LOW to write end 40 – ns
t
AW
Address setup to write end 40 – ns
t
HA
Address hold from write end 0 – ns
t
SA
Address setup to write start 0 – ns
t
PWE
WE pulse width 40 – ns
t
SD
Data setup to write end 25 – ns
t
HD
Data hold from write end 0 – ns
t
HZWE
WE LOW to high Z
[16, 17]
– 20 ns
t
LZWE
WE HIGH to low Z
[16]
10 – ns
Notes
14. In an earlier revision of this device, under a specific application condition, READ and WRITE operations were limited to switching of the chip enable signal as described
in the Application Note AN66311. However, the issue has been fixed and in production now, and hence, this Application Notes is no longer applicable. It is available
for download on our website as it contains information on the date code of the parts, beyond which the fix has been in production.
15. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of V
CC(typ)
/2, input pulse
levels of 0 to V
CC(typ)
, and output loading of the specified I
OL
/I
OH
as shown in Figure 2 on page 5.
16. At any temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any device.
17. t
HZOE
, t
HZCE
, and t
HZWE
transitions are measured when the output enter a high impedance state.
18. The internal write time of the memory is defined by the overlap of WE
, CE = V
IL
. All signals must be ACTIVE to initiate a write and any of these signals can terminate
a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
19. The minimum write cycle pulse width for Write Cycle No. 3 (WE
Controlled, OE LOW) should be equal to the sum of t
SD
and t
HZWE
.
