1. General description
The PCA9507 is a 2-wire serial bus extender providing 3.3 V to 5 V level shift that allows
up to 18 meters bus extension for reliable DDC, I
2
C-bus or SMBus applications. While
retaining all the operating modes and features of the I
2
C-bus system during the level
shifts, it also permits extension of the I
2
C-bus by providing bidirectional buffering for both
the data (SDA) and the clock (SCL) line as well as the rise time accelerator on port A
enabling the bus to drive a load up to 1400 pF or distance of 18 m on port A, and 400 pF
on port B. Using the PCA9507 enables the system designer to isolate bus capacitance to
meet HDMI DDC version 1.3 distance specification. The SDA and SCL pins are
overvoltage tolerant and are high-impedance when the PCA9507 is unpowered.
The port B drivers with static level offset behave much like the drivers on the PCA9515
device, while the port A drivers integrate the rise time accelerator, sink more current and
eliminate the static offset voltage. This results in a LOW on port B translating into a nearly
0 V LOW on port A. The static level offset design of the port B I/O drivers prevent them
from being connected to another device that has rise time accelerator including the
PCA9510, PCA9511, PCA9512, PCA9513, PCA9514, PCA9515, PCA9516A, PCA9517
(B-side), or PCA9518. The port A sides of two or more PCA9507s can be connected
together, however, to allow a star topography with port A on the common bus, and port A
can be connected directly to any other buffer with static or dynamic offset voltage. Multiple
PCA9507s can be connected in series, port A to port B, with no build-up in offset voltage
with only time of flight delays to consider. Rise time accelerator on port A is turned on
when input threshold is above 0.3V
CC(A)
.
The PCA9507 drivers are not enabled unless V
CC(A)
and V
CC(B)
are above 2.7 V. The EN
pin can also be used to turn the drivers on and off under system control. Caution should
be observed to only change the state of the enable pin when the bus is idle. The output
pull-down on the port B internal buffer LOW is set for approximately 0.5 V, while the input
threshold of the internal buffer is set about 70 mV lower (0.43 V). When the port B I/O is
driven LOW internally, the LOW is not recognized as a LOW by the input. This prevents a
lock-up condition from occurring.
2. Features
n 2 channel, bidirectional buffer isolates capacitance allowing 1400 pF on port A and
400 pF on port B
n Exceeds 18 meters (above the maximum distance for HDMI DDC)
n Rise time accelerator and normal I/O on port A
n Static level offset on port B
n Voltage level translation from 2.7 V to 5.5 V
n Upgrade replacement over PCA9517 for cable application
PCA9507
2-wire serial bus extender for HDMI DDC I
2
C-bus and SMBus
Rev. 01 — 7 February 2008 Product data sheet
