PCA9507_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 7 February 2008 4 of 20
NXP Semiconductors
PCA9507
2-wire serial bus extender for HDMI DDC I
2
C-bus and SMBus
When port B falls first and goes below 0.3V
CC(B)
the port A driver is turned on and port A
pulls down to 0 V. As port A falls below 0.3V
CC(A)
the port B pull-down pulls port B down to
about 0.5 V. Port B falls below 0.4 V because it is not possible to know who is driving the
port A LOW, so the PCA9507 direction control assumes that port A is controlling the part
unless port B falls below 0.4 V. When the port B voltage is 0.4 V the port A driver of the
PCA9507 is on and holds port A down nearly 0 V. As the port B voltage rises because the
external driver turns off, the port B voltage rises up to ~0.5 V because port A is LOW;
once port B rises to ~0.5 V the port A pull-down driver turns off. Then port A rises with a
rise time determined by the RC of port A when it crosses the port A threshold ~0.3V
CC(A)
the port B driver is turned off and the rising edge accelerator is turned on, which causes a
faster rising edge until it reaches the turn-off point for the rising edge accelerator
~0.7V
CC(A)
. Then it continues to rise at the slower rate determined by the RC of port A.
When the port B driver turns off, port B rises with the RC of port B.
V
CC(A)
powers the port A I/Os and the 0.3V
CC(A)
reference for port A as well as the port A
power good detect circuit. V
CC(B)
powers the rest of the chip including the port B I/Os and
the support functions. Figure 4 illustrates the threshold and I/O levels for port A and
port B.
6.1 Enable
The EN pin is active HIGH with an internal ~100 k pull-up to V
CC(B)
and allows the user
to select when the buffer is active. This can be used to isolate the line when the HDMI
DDC transmitter or receiver is not ready, or from a badly behaved slave on power-up until
after the system power-up reset. It should never change state during an I
2
C-bus operation
because disabling during a bus operation will hang the bus and enabling part way through
a bus cycle could confuse the I
2
C-bus parts being enabled. The enable pin should only
change state when the global bus and the buffer port are in an idle state to prevent system
failures.
6.2 Rise time accelerators
PCA9507 has rise time accelerators on port A only. During port A positive bus transitions
a current source is switched on to quickly slew the SDAA and SCLA lines HIGH once the
input level of 0.3V
CC(A)
is exceeded for the PCA9507 and turns off as the 0.7V
CC(A)
voltage is approached.
Fig 4. Port A and port B I/O levels
002aad435
0.3V
CC(B)
0.4 V
port B
V
CC(B)
port A
V
CC(A)
0.3V
CC(A)
0.5 V
0.7V
CC(A)
0 V
0 V
PCA9507_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 7 February 2008 5 of 20
NXP Semiconductors
PCA9507
2-wire serial bus extender for HDMI DDC I
2
C-bus and SMBus
6.3 Resistor pull-up value selection
6.3.1 Port A (SDAA and SCLA)
SDAA and SCLA are open-drain I/O that have rise time accelerators and strong pull-down.
When the inputs transition above 0.3V
CC(A)
, the rise time accelerator activates and boosts
the pull-up current during rising edge to meet the I
2
C-bus rise time specification when the
device drives a long cable or heavier capacitance load. The strong pull-down enables the
output to drive to nearly zero voltage for logic LOW. The selection for pull-up resistors are
defined in the HDMI DDC specification shown in Table 3. For HDMI transmitter
applications like digital video player, recorder, or set-top box, the pull-up resistor is in the
range of 1.5 kto 2 k. For HDMI receiver applications like in LCD TV or video card, the
pull-up resistor is 47 k on the SCLA line, and there is no pull-up on the SDAA line.
Please refer to Table 3, Figure 7 and Figure 8 for more details. Figure 5 shows the port A
pull-up resistor values (in k) versus capacitance load (in nF) for 5 V supply voltage
complied with 1 µs rise time per I
2
C-bus Standard-mode specification. The graph
contrasts a shaded and unshaded region. Any resistor value chosen within the unshaded
region would comply with 1 µs rise time, while any value chosen in the shaded region
would not.
Table 3. HDMI DDC pull-up resistors specification
Pin Where Minimum Maximum
SDAA at the source (DVD/STB) 1.5 k 2.0 k
at the sink (LCD TV) - -
SCLA at the source (DVD/STB) 1.5 k 2.0 k
at the sink (LCD TV) 47 kΩ±10 %
rise time = 1 µs; V
CC(A)
=5V
Fig 5. SDAA/SCLA line pull-up resistor versus load capacitance
C
L
(nF)
0 4.03.02.01.0
002aad620
4.5
6.5
2.5
8.5
10.5
R
PU
(k)
0.5
does not comply with
1 µs rise time
complies with
1 µs rise time
PCA9507_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 7 February 2008 6 of 20
NXP Semiconductors
PCA9507
2-wire serial bus extender for HDMI DDC I
2
C-bus and SMBus
6.3.2 Port B (SDAB and SCLB)
SDAB and SCLB are standard I
2
C-bus with static level offset that has no rise time
accelerator. The static level offset produces an output LOW of 0.5 V (typical) at 6 mA. As
with the standard I
2
C-bus system, pull-up resistors are required to provide the logic HIGH
levels. The size of these pull-up resistors depends on the system requirement, and should
meet the current sinking capability of the device that drives the buffer, as well as that of
the buffer. The minimum and maximum pull-up resistors are determined and the pull-up
resistor’s value is chosen to be within the minimum and maximum range.
Using Equation 1, calculate the minimum pull-up resistor value:
(1)
Where:
R
PU(min)
is the minimum pull-up resistor value for the open-drain SCLB and SDAB.
V
CC(B)(max)
is the maximum supply rail of the pull-up resistor.
0.4 V is the maximum V
OL
of the device that drives the buffer on logic LOW.
I
OL(max)
at V
OL
= 0.4 V is the maximum sink current of the device that drives the buffer
on logic LOW.
The maximum pull-up resistor should also be sized such that the RC time constant meets
the standard I
2
C-bus rise time, which is 1 µs for Standard-mode (100 kHz) or 300 ns for
Fast-mode (400 kHz). DDC bus complies with the I
2
C-bus Standard-mode and operates
below 100 kHz, and maximum rise time is 1 µs using a simplified RC equation.
Using Equation 2, calculate the maximum pull-up resistor value:
(2)
Where:
R
PU(max)
is the maximum allowable pull-up resistor on the SCLB and SDAB in order to
meet the I
2
C-bus rise time specification.
C
L(max)
is the maximum allowable capacitance load (include the capacitance of driver,
the line, and the buffer) in order to meet the rise time specification.
t
r
is the rise time specified as 1 µs (for bus speed 100 kHz or lower) and 300 ns (for bus
speed 400 kHz or lower).
The chosen pull-up resistor R
PU
is: R
PU(min)
R
PU
R
PU(max)
.
R
PU min()
V
CC B()max()
0.4 V
I
OL max()
-------------------------------------------------
=
R
PU max()
C
L max()
× 1.2 t
r
×=

PCA9507DP,118

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Interface - Signal Buffers, Repeaters LEVEL TRANSL I2C BUS
Lifecycle:
New from this manufacturer.
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