REV. C
AD9884A
–11–
GENERAL CONTROL
0A 7 DEMUX Output Port Select
A bit that determines whether all pixels are presented to a single
port (A), or alternating pixels are demultiplexed to Ports A and B.
DEMUX Function
0 All Data Goes to Port A
1 Alternate Pixels Go to Port A and Port B
When DEMUX = 0, Port B outputs are in a high impedance state.
The power-up default value is DEMUX = 1.
0A 6 PARALLEL Output Timing Select
Setting this bit to a Logic 1 delays data on Port A and the
DATACK output by one-half DATACK period so that the
rising edge of DATACK may be used to externally latch data
from both Port A and Port B. When this bit is set to a Logic 0,
the rising edge of DATACK may be used to externally latch
data from Port A only, and the DATACK rising edge may be
used to externally latch data from Port B.
PARALLEL Function
0 Data Alternates Between Ports
1 Simultaneous Data on Alternate DATACKs
When in single port mode (DEMUX = 0), this bit is ignored.
The power-up default value is PARALLEL = 1.
0A 5 HSPOL HSYNC Polarity
A bit that must be set to indicate the polarity of the HSYNC
signal that is applied to the HSYNC input.
HSPOL Function
0 Active LOW
1 Active HIGH
Active LOW is the traditional negative-going HSYNC pulse.
Sampling timing is based on the leading edge of HSYNC, which
is the FALLING edge. The Clamp Position, as determined by
CLPLACE, is measured from the trailing edge.
Active HIGH is inverted from the traditional HSYNC, with a
positive-going pulse. This means that sampling timing will be
based on the leading edge of HSYNC, which is now the RISING
edge, and clamp placement will count from the FALLING edge.
The device will operate more-or-less properly if this bit is set
incorrectly, but the internally generated clamp position, as
established by CLPOS, will not be placed as expected, which
may generate clamping errors.
The power-up default value is HSPOL = 1.
0A 4 CSTPOL COAST Polarity
A bit that must be set to indicate the polarity of the COAST
signal that is applied to the COAST input.
CSTPOL Function
0 Active LOW
1 Active HIGH
Active LOW means that the clock generator will ignore HSYNC
inputs when COAST is LOW, and continue operating at the
same nominal frequency until COAST goes HIGH.
Active HIGH means that the clock generator will ignore HSYNC
inputs when COAST is HIGH, and continue operating at the
same nominal frequency until COAST goes LOW.
The power-up default value is CSTPOL = 1.
0A 3 EXTCLMP Clamp Signal Source
A bit that determines the source of clamp timing.
EXTCLMP Function
0 Internally-generated clamp
1 Externally-provided clamp signal
A 0 enables the clamp timing circuitry controlled by CLPLACE
and CLDUR. The clamp position and duration is counted from
the trailing edge of HSYNC.
A 1 enables the external CLAMP input pin. The three channels
are clamped when the CLAMP signal is active. The polarity of
CLAMP is determined by the CLAMPOL bit.
The power-up default value is EXTCLMP = 0.
0A 2 CLAMPOL Clamp Signal Polarity
A bit that determines the polarity of the externally provided
CLAMP signal.
CLAMPOL Function
0 Active LOW
1 Active HIGH
A 0 means that the circuit will clamp when CLAMP is LOW,
and it will pass the signal to the ADC when CLAMP is HIGH.
A 1 means that the circuit will clamp when CLAMP is HIGH,
and it will pass the signal to the ADC when CLAMP is LOW.
The power-up default value is CLAMPOL = 1.
0A 1 EXTCLK External Clock Select
A bit that determines the source of the pixel clock.
EXTCLK Function
0 Internally generated clock
1 Externally provided clock signal
A 0 enables the internal PLL that generates the pixel clock from
an externally-provided HSYNC.
A 1 enables the external CKEXT input pin. In this mode, the
PLL Divide Ratio (PLLDIV) is ignored. The clock phase adjust
(PHASE) is still functional.
The power-up default value is EXTCLK = 0.
