REV. C
AD9884A
–18–
Two things happen to Horizontal Sync in the AD9884A. First,
HSOUT is always produced in an active HIGH state: that is,
the leading edge of HSOUT is always a RISING edge. Then,
HSOUT is aligned with DATACK and the data outputs. This is
the sync signal that should be used to drive the rest of the dis-
play system.
The trailing edge of HSOUT is NOT time-aligned: it remains
linked to the incoming HSYNC. Refer to the timing diagrams
for HSOUT leading edge placement. HSOUT trailing edge is
coincident with HSYNC input trailing edge. There can be no
guarantee of the timing relationship between the HSOUT trail-
ing edge and DATACK. Therefore, the leading edge of HSOUT
should be used for all display system timing.
HSOUT is forced LOW at midline, whether or not the incom-
ing HSYNC trailing edge has arrived. If HSOUT exhibits a
50% duty cycle (while HSYNC input does not) it is an indica-
tion that the HSPOL bit is incorrectly set. This characteristic
can be used to produce an HSOUT with synchronous leading
and trailing edges by programming HSPOL to use the trailing
edge of HSYNC instead of the leading edge. In this case, if the
internal clamp function is used, be aware that the clamp posi-
tion is now measured from the LEADING edge of HSYNC,
and program it accordingly.
COAST Timing
In most computer systems, the HSYNC signal is provided con-
tinuously on a dedicated wire. In these systems, the COAST
input and function are unnecessary, and should not be used.
In some systems, however, HSYNC is disturbed during the
Vertical Sync period (VSYNC). In some cases, HSYNC pulses
disappear. In other systems, such as those that employ Compos-
ite Sync (CSYNC) signals or embed Sync On Green (SOG),
HSYNC includes equalization pulses or other distortions during
VSYNC. To avoid upsetting the clock generator during VSYNC,
it is important to ignore these distortions. If the pixel clock PLL
sees extraneous pulses, it will attempt to lock to this new fre-
quency, and will have changed frequency by the end of the
VSYNC period. It then will take a few lines of correct HSYNC
timing to recover at the beginning of a new frame, resulting in a
“tearing” of the image at the top of the display.
The COAST input is provided to eliminate this problem. It is
an asynchronous input that disables the PLL input and allows
the clock to free-run at its then-current frequency. The PLL can
free-run for several lines without significant frequency drift.
COAST can be driven directly from a VSYNC input, or it can
be provided by the graphics controller.
TIMING
The following timing diagrams show the operation of the
AD9884A in all clock modes. The part establishes timing by
having the sample that corresponds to the pixel digitized when
the leading edge of HSYNC occurs sent to the “A” data port (to
the B data port if 0Dh, Bit 4 = 1). In Dual Channel mode, the
next sample is sent to the “B” port (to the A data port if 0Dh,
Bit 4 = 1). Subsequent samples are alternated between the “A”
and “B” data ports. In Single Channel mode, data is only sent
to the “A” data port, and the “B” port is placed in a high im-
pedance state.
When operating in Dual Channel mode, since the first pixel
after HSYNC is always sent to the A port, there are situations
where the first DESIRED pixel (the first active pixel of a line)
may appear on the B port. If the graphics controller or memory
buffer requires that the first pixel appear on the A port, the
OUTPHASE control bit will swap the data to the A and B ports.
The Output Data Clock signal is created so that its rising edge
always occurs between “A” data transitions, and can be used to
latch the output data externally. The HSYNC output is pipelined
with the data in a fixed timing relationship between the two in
all Single Channel modes.
There is a pipeline in the AD9884A, which must be flushed
before valid data becomes available. In all single channel
modes, four data sets are presented before valid data is avail-
able. In all dual channel modes, two data sets are presented
before valid “A” port data is available.
t
PER
t
DCYCLE
t
SKEW
DATACK
DATACK
DATA
HSOUT
Figure 12. Output Timing
Horizontal Sync Timing
Horizontal Sync is processed in the AD9884A to eliminate
ambiguity in the timing of the leading edge with respect to the
phase-delayed pixel clock and data.
The HSYNC input is used as a reference to generate the pixel
sampling clock. The sampling phase can be adjusted, with
respect to HSYNC, through a full 360° in 32 steps via the PHASE
register (to optimize the pixel sampling time). Display systems
use HSYNC to align memory and display write cycles, so it is
important to have a stable timing relationship between HSOUT
and DATACK.
