REV. C
AD9884A
–7–
PIN FUNCTION DESCRIPTIONS (continued)
Pin Name Function
OUTPUTS
D
R
A
7–0
Data Output, Red Channel, Port A
D
R
B
7–0
Data Output, Red Channel, Port B
D
G
A
7–0
Data Output, Green Channel, Port A
D
G
B
7–0
Data Output, Green Channel, Port B
D
B
A
7–0
Data Output, Blue Channel, Port A
D
B
B
7–0
Data Output, Blue Channel, Port B
The main data outputs. Bit 7 is the MSB. Each channel has two ports. When the part is operated in Single Chan-
nel mode (DEMUX = 0), all data are presented to Port A, and Port B is placed in a high impedance state. Pro-
gramming DEMUX to 1 establishes Dual Channel mode, wherein alternate pixels are presented to Port A and
Port B of each channel. These will appear simultaneously, two pixels presented at the time of every second input
pixel, when PAR is set to 1 (parallel mode). When PAR = 0, pixel data appear alternately on the two ports, one
new sample with each incoming pixel (interleaved mode). In Dual Channel mode, the first pixel sampled after
HSYNC is routed to Port A. The second pixel goes to Port B, the third to A, etc. The delay from pixel sampling
time to output is fixed. When the sampling time is changed by adjusting the PHASE register, the output timing is
shifted as well. The DATACK, DATACK and HSOUT outputs are also moved, so the timing relationship among
the signals is maintained.
DATACK Data Output Clock
DATACK Data Output Clock Complement
Differential data clock output signals to be used to strobe the output data and HSOUT into external logic. They
are produced by the internal clock generator and are synchronous with the internal pixel sampling clock. When the
AD9884A is operated in Single Channel mode, the output frequency is equal to the pixel sampling frequency.
When operating in Dual Channel mode, the Data Output Clock and the Output Data are presented at one-half the
pixel rate. When the sampling time is changed by adjusting the PHASE register, the output timing is shifted as
well. The Data, DATACK, DATACK and HSOUT outputs are all moved, so the timing relationship among the
signals is maintained. Either or both signals may be used, depending on the timing mode and interface design
employed.
HSOUT Horizontal Sync Output
A reconstructed and phase-aligned version of the HSYNC input. This signal is always active HIGH. By maintain-
ing alignment with DATACK, DATACK, and Data, data timing with respect to horizontal sync can always be
clearly determined.
SOGOUT Sync On Green Slicer Output
The output of the Sync On Green slicer comparator. When SOGIN is presented with a dc-coupled ground-referenced
analog graphics signal containing composite sync, SOGOUT will produce a digital composite sync signal. This
signal gets no other processing on the AD9884A. The SOG slicer comparator continues to operate when the
AD9884A is put into a power-down state.
CONTROL
SDA Serial Data I/O
Bidirectional data port for the serial interface port.
SCL Serial Interface Clock
Clock input for the serial interface port.
A
1–0
Serial Port Address LSBs
The two least significant bits of the serial port address are set by the logic levels on these pins. Connect a pin to
ground to set the address bit to 0. Tie it HIGH (to V
D
through 10 kΩ) to set the address bit to 1. Using these pins,
the serial address may be set to any value from 98h to 9Fh. Up to four AD9884As may be used on the same serial
bus by appropriately setting these bits. They can also be used to change the AD9884A address if a conflict is found
with another device on the bus.
PWRDN Power-Down Control Input
Bringing this pin LOW puts the AD9884A into a very low power dissipation mode. The output buffers are placed
in a high impedance state. The clock generator is stopped. The control register contents are maintained. The Sync
On Green Slicer (SOGOUT) and internal reference continue to function.
