8
FN7445.0
December 13, 2006
Pin Descriptions
PIN # PIN NAME PIN DESCRIPTION
1 DRVN Negative LDO base drive; open drain of an internal P-Channel MOSFET.
2 DELB Active low control output for optional delay control for external A
VDD
P-Channel FET; when fault is detected, this pin
goes to high.
3 FBW Negative LDO voltage feedback input pin; regulates to 0.2V nominal.
4 VCC1 Supply input, connect to V
IN
.
5FBBA
VDD
regulator voltage feedback input pin; regulates to 1.2V nominal.
6 ISADJB Current feedback adjust for A
VDD
.
7 ILADJB With a resistor connected from this pin to GND sets the current limit of the external N-channel FET for A
VDD.
8CINTBA
VDD
integrator output, connect 2.2nF to analog GND.
9 DRVB Gate driver output for the external N-Channel switch.
10 PGNDB Power GND for A
VDD
.
11 VHIB Internal Drive of Boost controller, Connect to VDCP.
12 NC
13 ISINB Sense the drain voltage of the external N-channel FET and connected to the internal current limit comparator.
14 VIN Main supply input.
15 EN Enable pin; high enable, low disabled.
16 VHIL V
LOGIC
boost strap mode.
17 LX V
LOGIC
switch connection.
18 DRVL Gate driver output for external N-channel switch.
19 PGNDP Power GND.
20 FBL V
LOGIC
regulator voltage feedback pin; regulates to 1.2V nominal.
21 ILADJL With resistor connected from this pin to GND sets the current limit of the external N-channel FET.
22 CINTL V
LOGIC
integrator output, connect 2.2nF to analog GND.
23 ISADJL Current feedback adjust for V
LOGIC
.
24 VDC Positive supply for all internal analog circuits.
25 VDCP Positive supply for external N-Channel FET gate drives.
26 NC
27 DRVP Positive LDO base drive; open drain of an internal N-Channel MOSFET.
28 NC
29 ACGND Low noise signal ground.
30 VREF Bandgap voltage bypass terminal; bypass with a 0.1µF to analog GND; can be used as charge pump reference.
31 FBP Positive LDO voltage feedback input pin; regulates to 1.2V nominal.
32 CC2 Supply input, connect to V
IN
.
33 CDLY With a capacitor connect from this pin to GND, sets the delay time for start-up sequence and fault detection timeout.
34 CTL Input control for switch output.
35 ENL Enable pin for V
LOGIC
high enable; low disabled.
36 DRN Lower reference voltage for switch output.
37 COM Switch output; when CTL = 1, COM is connected to SRC through a 15 resistor, when CT: = 0, COM is connected
to DRN through a 30 resistor.
38 SRC Upper reference voltage for switch output.
ISL97522
