CY7C1461AV33
CY7C1463AV33
Document Number: 38-05356 Rev. *O Page 10 of 24
Truth Table
The truth table for CY7C1461AV33/CY7C1463AV33 follows.
Operation
[1, 2, 3, 4, 5, 6, 7]
Address Used
CE
1
CE
2
CE
3
ZZ ADV/LD WE BW
X
OE CEN CLK DQ
Deselect Cycle None H X X L L X X X L L->H Tristate
Deselect Cycle None X X H L L X X X L L->H Tristate
Deselect Cycle None X L X L L X X X L L->H Tristate
Continue Deselect Cycle None X X X L H X X X L L->H Tristate
Read Cycle (Begin Burst) External L H L L L H X L L L->H Data Out (Q)
Read Cycle (Continue Burst) Next X X X L H X X L L L->H Data Out (Q)
NOP/Dummy Read
(Begin Burst)
External L H L L L H X H L L->H Tristate
Dummy Read (Continue Burst) Next X X X L H X X H L L->H Tristate
Write Cycle (Begin Burst) External L H L L L L L X L L->H Data In (D)
Write Cycle (Continue Burst) Next X X X L H X L X L L->H Data In (D)
NOP/Write Abort (Begin Burst) None L H L L L L H X L L->H Tristate
Write Abort (Continue Burst) Next X X X L H X H X L L->H Tristate
Ignore Clock Edge (Stall) Current X X X L X X X X H L->H –
Sleep Mode None XXXH X XXXXX Tristate
Notes
1. X = “Don't Care.” H = logic HIGH, L = logic LOW. BW
x = L signifies at least one byte write select is active, BWx = Valid signifies that the desired byte write selects
are asserted, see truth table for details.
2. Write is defined by BW
X
, and WE. See truth table for read or write.
3. When a write cycle is detected, all IOs are tristated, even during byte writes.
4. The DQs and DQP
X
pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. CEN
= H, inserts wait states.
6. Device powers up deselected and the IOs in a tri-state condition, regardless of OE
.
7. OE
is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP
X
= Tri-state when OE is
inactive or when the device is deselected, and DQs and DQP
X
= data when OE is active.
