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CY7C1461AV33-133AXI

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CY7C1461AV33
CY7C1463AV33
Document Number: 38-05356 Rev. *O Page 12 of 24
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ............................... –65 C to +150 C
Ambient Temperature with
Power Applied ......................................... –55 C to +125 C
Supply Voltage on V
DD
Relative to GND .....–0.5 V to +4.6 V
Supply Voltage on V
DDQ
Relative to GND .... –0.5 V to +V
DD
DC Voltage Applied to Outputs
in Tri-State ........................................–0.5 V to V
DDQ
+ 0.5 V
DC Input Voltage ................................–0.5 V to V
DD
+ 0.5 V
Current into Outputs (LOW) ........................................20 mA
Static Discharge Voltage
(MIL-STD-883, Method 3015) ................................ > 2001 V
Latch Up Current .................................................. > 200 mA
Operating Range
Range
Ambient
Temperature
V
DD
V
DDQ
Commercial 0 °C to +70 °C
3.3 V– 5% /
+ 10%
2.5 V – 5% to
V
DD
Industrial –40 °C to +85 °C
Electrical Characteristics
Over the Operating Range
Parameter
[10, 11]
Description Test Conditions Min Max Unit
V
DD
Power supply voltage 3.135 3.6 V
V
DDQ
I/O supply voltage for 3.3 V I/O 3.135 V
DD
V
for 2.5 V I/O 2.375 2.625 V
V
OH
Output HIGH voltage for 3.3 V I/O, I
OH
= –4.0 mA 2.4 – V
for 2.5 V I/O, I
OH
= –1.0 mA 2.0 – V
V
OL
Output LOW voltage for 3.3 V I/O, I
OL
= 8.0 mA – 0.4 V
for 2.5 V I/O, I
OL
= 1.0 mA – 0.4 V
V
IH
Input HIGH voltage
[10]
for 3.3 V I/O 2.0 V
DD
+ 0.3 V V
for 2.5 V I/O 1.7 V
DD
+ 0.3 V V
V
IL
Input LOW voltage
[10]
for 3.3 V I/O –0.3 0.8 V
for 2.5 V I/O –0.3 0.7 V
I
X
Input leakage current except ZZ
and MODE
GND V
I
V
DDQ
–5 5 A
Input current of MODE Input = V
SS
–30 – A
Input = V
DD
–5A
Input current of ZZ Input = V
SS
–5 – A
Input = V
DD
–30A
I
OZ
Output leakage current GND V
I
V
DDQ,
Output Disabled –5 5 A
I
DD
V
DD
operating supply current V
DD
= Max, I
OUT
= 0 mA,
f = f
MAX
= 1/t
CYC
7.5 ns cycle,
133 MHz
–310mA
I
SB1
Automatic CE power down
current – TTL Inputs
V
DD
= Max, Device Deselected,
V
IN
V
IH
or V
IN
V
IL
; f = f
MAX
,
Inputs Switching
7.5 ns cycle,
133 MHz
–180mA
I
SB2
Automatic CE power down
current – CMOS Inputs
V
DD
= Max, Device Deselected,
V
IN
 0.3 V or V
IN
> V
DD
– 0.3 V,
f = 0, Inputs Static
7.5 ns cycle,
133 MHz
–120mA
I
SB3
Automatic CE power down
current – CMOS Inputs
V
DD
= Max, Device Deselected,
V
IN
0.3 V or V
IN
> V
DDQ
– 0.3 V
f = f
MAX
, Inputs Switching
7.5 ns cycle,
133 MHz
–180mA
I
SB4
Automatic CE Power down
current – TTL Inputs
V
DD
= Max, Device Deselected,
V
IN
V
DD
– 0.3 V or V
IN
0.3 V,
f = 0, Inputs Static
7.5 ns cycle,
133 MHz
–135mA
CY7C1461AV33
CY7C1463AV33
Document Number: 38-05356 Rev. *O Page 13 of 24
Capacitance
Parameter
[12]
Description Test Conditions
100-pin TQFP
Max
Unit
C
IN
Input capacitance T
A
= 25 C, f = 1 MHz,
V
DD
= 3.3 V, V
DDQ
= 2.5 V
6.5 pF
C
CLK
Clock input capacitance 3 pF
C
IO
Input/Output capacitance 5.5 pF
Thermal Resistance
Parameter
[12]
Description Test Conditions
100-pin TQFP
Package
Unit
JA
Thermal resistance
(junction to ambient)
Test conditions follow standard test methods and
procedures for measuring thermal impedance, according
to EIA/JESD51.
25.21 °C/W
JC
Thermal resistance
(junction to case)
2.28 °C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
OUTPUT
R = 317
R = 351
5pF
INCLUDING
JIG AND
SCOPE
(a) (b)
OUTPUT
R
L
= 50
Z
0
= 50
V
T
= 1.5 V
3.3 V
ALL INPUT PULSES
V
DDQ
GND
90%
10%
90%
10%
1ns
1ns
(c)
OUTPUT
R = 1667
R = 1538
5pF
INCLUDING
JIG AND
SCOPE
(a) (b)
OUTPUT
R
L
= 50
Z
0
= 50
V
T
= 1.25 V
2.5 V
ALL INPUT PULSES
V
DDQ
GND
90%
10%
90%
10%
1ns
1ns
(c)
3.3 V I/O Test Load
2.5 V I/O Test Load
Note
12. Tested initially and after any design or process change that may affect these parameters.
CY7C1461AV33
CY7C1463AV33
Document Number: 38-05356 Rev. *O Page 14 of 24
Switching Characteristics
Over the Operating Range
Parameter
[13, 14]
Description
133 MHz
Unit
Min Max
t
POWER
[15]
1 – ms
Clock
t
CYC
Clock Cycle Time 7.5 – ns
t
CH
Clock HIGH 2.5 – ns
t
CL
Clock LOW 2.5 – ns
Output Times
t
CDV
Data Output Valid after CLK Rise – 6.5 ns
t
DOH
Data Output Hold after CLK Rise 2.5 – ns
t
CLZ
Clock to Low Z
[16, 17, 18]
2.5 – ns
t
CHZ
Clock to High Z
[16, 17, 18]
– 3.8 ns
t
OEV
OE LOW to Output Valid – 3.0 ns
t
OELZ
OE LOW to Output Low Z
[16, 17, 18]
0 – ns
t
OEHZ
OE HIGH to Output High Z
[16, 17, 18]
– 3.0 ns
Setup Times
t
AS
Address Setup before CLK Rise 1.5 – ns
t
ALS
ADV/LD Setup before CLK Rise 1.5 – ns
t
WES
WE, BW
X
Setup before CLK Rise 1.5 – ns
t
CENS
CEN
Setup before CLK Rise 1.5 – ns
t
DS
Data Input Setup before CLK Rise 1.5 – ns
t
CES
Chip Enable Setup before CLK Rise 1.5 – ns
Hold Times
t
AH
Address Hold after CLK Rise 0.5 – ns
t
ALH
ADV/LD Hold after CLK Rise 0.5 – ns
t
WEH
WE, BW
X
Hold after CLK Rise 0.5 – ns
t
CENH
CEN Hold after CLK Rise 0.5 – ns
t
DH
Data Input Hold after CLK Rise 0.5 – ns
t
CEH
Chip Enable Hold after CLK Rise 0.5 – ns
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CY7C1461AV33-133AXI

Mfr. #:
Buy CY7C1461AV33-133AXI
Manufacturer:
Cypress Semiconductor
Description:
SRAM 36Mb 3.3V 133Mhz 1Mx36 Flow-Thru SRAM
Lifecycle:
New from this manufacturer.
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