AD7303–Typical Performance Characteristics
–6–
REV. 0
V
DD
= +5V AND +3V
INTERNAL REFERENCE
T
A
= 258C
DAC LOADED WITH 00HEX
SINK CURRENT – mA
V
OUT
– mV
800
0
08246
720
400
249
160
80
640
560
320
480
Figure 3. Output Sink Current Capa-
bility with V
DD
= 3 V and V
DD
= 5 V
REFERENCE VOLTAGE – Volts
ERROR – LSBs
0.5
0
1 1.2 2.8
1.4 1.6 1.8 2.2 2.4 2.62
0.45
0.25
0.15
0.1
0.05
0.4
0.35
0.2
0.3
V
DD
= +5V
T
A
= 258C
INL ERROR
DNL ERROR
Figure 6. Relative Accuracy vs.
External Reference
FREQUENCY – kHz
ATTENUATION – dB
1 10 10000100 1000
10
5
–40
0
–5
–10
–15
–20
–25
–30
–35
V
DD
= +5V
T
A
= 25°C
EXTERNAL SINE WAVE REFERENCE
DAC REGISTER LOADED WITH FFHEX
Figure 9. Large Scale Signal
Frequency Response
SOURCE CURRENT – mA
V
OUT
– Volts
02 846
5
4.92
4.2
4.84
4.76
4.68
4.6
4.52
4.44
4.36
4.28
V
DD
= +5V
T
A
= 25°C
INTERNAL REFERENCE
DAC REGISTER LOADED WITH FFHEX
Figure 4. Output Source Current
Capability with V
DD
= 5 V
–60 –40 –20 0 20 40 60 80 100 120 140
TEMPERATURE – 8C
5
3.5
2
I
DD
– mA
4.5
4
3
2.5
LOGIC INPUTS = V
DD
OR GND
INTERNAL REFERENCE
V
DD
= +5V
LOGIC INPUTS = V
IH
OR V
IL
Figure 7. Supply Current vs.
Temperature
T
SYNC
V
OUT
V
DD
= +3V
INTERNAL VOLTAGE REFERENCE
FULL SCALE CODE CHANGE 00H-FFH
T
A
= 25°C
1
3
2
V
OUT
CH1 5V, CH2 1V, CH3 20mV
TIME BASE = 200ns/div
Figure 10. Full-Scale Settling Time
SOURCE CURRENT – mA
3.5
1
01 8234567
3.25
2.5
2.25
1.75
1.25
3
2.75
2
1.5
V
OUT
– Volts
V
DD
= +3V
T
A
= 25°C
INTERNAL REFERENCE
DAC REGISTER LOADED WITH FFHEX
Figure 5. Output Source Current
Capability with V
DD
= 3 V
V
DD
– Volts
I
DD
– mA
5.5
1.5
5
3.5
3
2.5
2
4.5
4
2.5 3 5.5
3.5 4 4.5 5
LOGIC INPUTS = V
DD
OR GND
LOGIC INPUTS = V
IH
OR V
IL
T
A
= 25°C
INTERNAL REFERENCE
Figure 8. Supply Current vs.
Supply Voltage
SYNC
V
OUT
POWER UP TIME
V
DD
= +5V
INTERNAL REFERENCE
BOTH DACS IN POWER DOWN INITIALLY
1
2
CH1 = 2V/div, CH2 = 5V/div,
TIME BASE = 2µs/div
Figure 11. Exiting Power-Down (Full
Power-Down)
AD7303
–7–
REV. 0
T
DAC A = NORMAL OPERATION
DAC B INITIALLY IN POWER
DOWN
1
2
V
OUT
B
SYNC
DAC B EXITING
POWER DOWN
CH1 2V, CH2 5V, M 500ns
V
DD
= +5V
INTERNAL REFERENCE
T
A
= 258C
Figure 12. Exiting Power-Down
(Partial Power-Down)
Input Code (10 to 245)
INL ERROR – LSB
0 25532 64 96 128 160 192 224
DAC B
DAC A
V
DD
= +5V
INTERNAL REFERENCE
5k 100pF LOAD
LIMITED CODE RANGE (10-245)
T
A
= 25°C
–0.5
0.4
0.1
–0.1
–0.3
–0.4
0.3
0.2
0
–0.2
0.5
Figure 15. Integral Linearity Plot
I
DD
– mA
050.5 1 1.5 2 2.5 3 3.5 4 4.5
4
0
7
6
2
1
5
3
V
DD
= +5V
V
DD
= +3V
Figure 13. Supply Current vs.
Logic Input Voltage
V
DD
= +5V
INTERNAL REFERENCE
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
–60 –40 –20 0 20 40 60 80 100 120 140
INL ERROR – LSB
TEMPERATURE – 8C
Figure 16. Typical INL vs.
Temperature
2
1
V
OUT
CH1 5.00V, CH2 50.0mV, M 250ns
SYNC
V
DD
= +5V
INTERNAL VOLTAGE
REFERENCE
10 LSB STEP CHANGE
T
A
= 258C
Figure 14. Small Scale Settling
Time
Figure 17. Typical DNL vs.
Temperature
TEMPERATURE – 8C
500
400
200
100
0
300
–50 0
50 100 150
V
DD
= +5.5V
V
IL
AND V
IH
= 0V OR V
DD
POWER-DOWN CURRENT – nA
–25 25 75 125
Figure 19. Power-Down Current vs.
Temperature
V
DD
= +5V
0.6
0.4
0.2
0
–60 –40 –20 0 20 40 60 80 100 120 140
TEMPERATURE – 8C
INT REFERENCE ERROR – 6%
0.8
1.0
Figure 18. Typical Internal Reference
Error vs. Temperature
AD7303
–8–
REV. 0
GENERAL DESCRIPTION
D/A Section
The AD7303 is a dual 8-bit voltage output digital-to-analog
converter. The architecture consists of a reference amplifier and
a current source DAC, followed by a current-to-voltage con-
verter capable of generating rail-to-rail voltages on the output of
the DAC. Figure 20 shows a block diagram of the basic DAC
architecture.
REFERENCE
AMPLIFIER
OUTPUT
AMPLIFIER
V
O
A/B
V
DD
REF
AD7303
CURRENT
DAC
11.7k
30k
11.7k
30k
Figure 20. DAC Architecture
Both DAC A and DAC B outputs are internally buffered and
these output buffer amplifiers have rail-to-rail output character-
istics. The output amplifier is capable of driving a load of 10 k
to both V
DD
and ground and 100 pF to ground. The reference
selection for the DAC can be either internally generated from
V
DD
or externally applied through the REF pin. Reference
selection is via a bit in the control register. The range on the
external reference input is from 1.0 V to V
DD
/2. The output
voltage from either DAC is given by:
V
O
A/B = 2 × V
REF
× (N/256)
where:
V
REF
is the voltage applied to the external REF pin or
V
DD
/2 when the internal reference is selected.
N is the decimal equivalent of the code loaded to the DAC
register and ranges from 0 to 255.
Reference
The AD7303 has the facility to use either an external reference
applied through the REF pin or an internal reference generated
from V
DD
. Figure 21 shows the reference input arrangement
where the internal V
DD
/2 has been selected.
30k
30k
REFERENCE
AMPLIFIER
AD7303
REF
0.1µF
V
DD
INT/EXT
Figure 21. Reference Input
When the internal reference is selected during the write to the
DAC, both switches are closed and V
DD
/2 is generated and
applied to the reference amplifier. This internal V
DD
/2 reference
appears at the reference pin as an output voltage for decoupling
purposes. When using the internal reference, external references
should not be connected to the REF Pin. This internal V
DD
/2
reference appears at the reference pin as an output voltage for
decoupling purposes. When using the internal reference, external
references should not be connected to the REF pin. If external ref-
erence is selected, both switches are open and the externally
applied voltage to the REF pin is applied to the reference amplifier.
Decoupling capacitors applied to the REF pin decouple both
the internal reference and external reference. In noisy environ-
ments it is recommended that a 0.1 µF capacitor be connected
to the REF pin to provide added decoupling even when the in-
ternal reference is selected.
Analog Outputs
The AD7303 contains two independent voltage output DACs
with 8-bit resolution and rail-to-rail operation. The output buffer
provides a gain of two at the output. Figures 3 to 5 show the sink
and source capabilities of the output amplifier. The slew rate of the
output amplifier is typically 8 V/µs and has a full-scale settling to 8
bits with a 100 pF capacitive load in typically 1.2 µs.
The input coding to the DAC is straight binary. Table I shows
the binary transfer function for the AD7303. Figure 22 shows
the DAC transfer function for binary coding. Any DAC output
voltage can ideally be expressed as:
V
OUT
= 2 × V
REF
(N/256)
where:
N is the decimal equivalent of the binary input code.
N ranges from 0 to 255.
V
REF
is the voltage applied to the external REF pin when
the external reference is selected and is V
DD
/2 if the
internal reference is used.
Table I. Binary Code Table for AD7303 DAC
Digital Input
MSB . . . LSB Analog Output
1111 1111 2 × 255/256 × V
REF
V
1111 1110 2 × 254/256 × V
REF
V
1000 0001 2 × 129/256 × V
REF
V
1000 0000 V
REF
V
0111 1111 2 × 127/256 × V
REF
V
0000 0001 2 × V
REF
/256 V
0000 0000 0 V
2.V
REF
V
REF
0
DAC OUTPUT VOLTAGE
00 01
DAC INPUT
CODE
FF80 81 FE7F
Figure 22. DAC Transfer Function

AD7303BNZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC 2.7-5.5V Serial Inpt Dual VOut 8B
Lifecycle:
New from this manufacturer.
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