DS1870
LDMOS RF Power-Amplifier Bias
Controller
____________________________________________________________________ 25
setup and hold time requirements (Figure 3). Data is
shifted into the device during the rising edge of the SCL.
Bit read: At the end a write operation, the master must
release the SDA bus line for the proper amount of setup
time (Figure 3) before the next rising edge of SCL dur-
ing a bit read. The device shifts out each bit of data on
SDA at the falling edge of the previous SCL pulse and
the data bit is valid at the rising edge of the current
SCL pulse. Remember that the master generates all
SCL clock pulses, including when it is reading bits from
the slave.
Acknowledgement (ACK and NACK): An acknowl-
edgement (ACK) or not acknowledge (NACK) is always
the 9th bit transmitted during a byte transfer. The
device receiving data (the master during a read or the
slave during a write operation) performs an ACK by
transmitting a zero during the 9th bit. A device per-
forms a NACK by transmitting a one during the 9th bit.
Timing (Figure 3) for the ACK and NACK is identical to
all other bit writes. An ACK is the acknowledgment that
the device is properly receiving data. A NACK is used
to terminate a read sequence or as an indication that
the device is not receiving data.
Byte write: A byte write consists of 8 bits of information
transferred from the master to the slave (most signifi-
cant bit first) plus a 1-bit acknowledgement from the
slave to the master. The 8 bits transmitted by the mas-
ter are done according to the bit write definition and the
acknowledgement is read using the bit read definition.
Byte read: A byte read is an 8-bit information transfer
from the slave to the master plus a 1-bit ACK or NACK
from the master to the slave. The 8 bits of information
that are transferred (most significant bit first) from the
slave to the master are read by the master using the bit
read definition above, and the master transmits an ACK
using the bit write definition to receive additional data
bytes. The master must NACK the last byte read to ter-
minated communication so the slave will return control
of SDA to the master.
Slave address byte: Each slave on the I
2
C bus
responds to a slave addressing byte sent immediately
following a start condition. The slave address byte
(Figure 4) contains the slave address in the most signifi-
cant 7 bits and the R/W bit in the least significant bit.
The DS1870’s slave address is 1010A
2
A
1
A
0
(binary),
where A
2
, A
1
, and A
0
are the values of the address
pins. The address pins allow the device to respond to
one of eight possible slave addresses. By writing the
correct slave address with R/W = 0, the master indi-
cates it will write data to the slave. If R/W = 1, the mas-
ter will read data from the slave. If an incorrect slave
address is written, the DS1870 assumes the master is
communicating with another I
2
C device and ignores the
communications until the next start condition is sent.
Memory address: During an I
2
C write operation, the
master must transmit a memory address to identify the
memory location where the slave is to store the data.
The memory address is always the second byte trans-
mitted during a write operation following the slave
address byte.
I
2
C Communication
Writing a single byte to a slave: The master must
generate a start condition, write the slave address byte
(R/W = 0), write the memory address, write the byte of
data, and generate a stop condition. Remember the
master must read the slave’s acknowledgement during
all byte write operations.
Writing multiple bytes to a slave: To write multiple
bytes to a slave, the master generates a start condition,
writes the slave address byte (R/W = 0), writes the
memory address, writes up to 8 data bytes, and gener-
ates a stop condition.
The DS1870 writes 1 to 8 bytes (1 page or row) with a
single write transaction. This is internally controlled by
an address counter that allows data to be written to
consecutive addresses without transmitting a memory
address before each data byte is sent. The address
counter limits the write to one 8-byte page (one row of
the memory map). Attempts to write to additional pages
of memory without sending a stop condition between
pages results in the address counter wrapping around
to the beginning of the present row.
Example: A 3-byte write starts at address 06h and
writes three data bytes (11h, 22h, and 33h) to three
“consecutive” addresses. The result is that addresses
06h and 07h would contain 11h and 22h, respectively,
and the third data byte, 33h, would be written to
address 00h.
To prevent address wrapping from occurring, the mas-
ter must send a stop condition at the end of the page,
then wait for the bus-free or EEPROM-write time to
elapse. Then the master can generate a new start con-
