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6042DS–ATARM–14-Dec-06
AT91SAM7A3
9.2 Reset Controller
The Reset Controller is based on three power-on reset cells. It gives the status of the last reset,
indicating whether it is a general reset, a wake-up reset, a software reset, a user reset or a
watchdog reset. In addition, it controls the internal resets and the NRST pin output. It shapes a
signal on the NRST line, guaranteeing that the length of the pulse meets any requirement.
9.3 Clock Generator
The Clock Generator embeds one low-power RC Oscillator, one Main Oscillator and one PLL
with the following characteristics:
– RC Oscillator ranges between 22 KHz and 42 KHz
– Main Oscillator frequency ranges between 3 and 20 MHz
– Main Oscillator can be bypassed
– PLL output ranges between 80 and 220 MHz
It provides SLCK, MAINCK and PLLCK.
Figure 9-2. Clock Generator Block Diagram
9.4 Power Management Controller
The Power Management Controller uses the Clock Generator outputs to provide:
– the Processor Clock PCK
– the Master Clock MCK
– the USB Clock UDPCK
– all the peripheral clocks, independently controllable
– four programmable clock outputs
The Master Clock (MCK) is programmable from a few hundred Hz to the maximum operating fre-
quency of the device.
The Processor Clock (PCK) switches off when entering processor idle mode, thereby reducing
power consumption while waiting an interrupt.
Power
Management
Controller
XIN
XOUT
PLLRC
Slow Clock
SLCK
Main Clock
MAINCK
PLL Clock
PLLCK
ControlStatus
Embedded
RC
Oscillator
Main
Oscillator
PLL and
Divider
Clock Generator
