NTD6415AN, NVD6415AN
http://onsemi.com
4
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 7. Capacitance Variation
T
J
= 25°C
V
GS
= 0 V
C
iss
C
oss
C
rss
0
2
4
6
8
10
0 5 10 15 20 25 30
0
20
40
60
80
100
Q
T
Q
ds
Q
gs
Q
g
, TOTAL GATE CHARGE (nC)
Figure 8. Gate−to−Source Voltage and
Drain−to−Source Voltage versus Total Charge
I
D
= 23 A
T
J
= 25°C
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
V
, DRAIN−TO−SOURCE VOLTAGE (V
V
DS
V
GS
1
10
100
1000
1 10 100
R
G
, GATE RESISTANCE (W)
Figure 9. Resistive Switching Time Variation
versus Gate Resistance
t
d(off)
t
f
t
r
t
d(on)
V
DS
= 80 V
I
D
= 23 A
V
GS
= 10 V
0
5
10
15
20
25
0.4 0.5 0.6 0.7 0.8 0
V
SD
, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 10. Diode Forward Voltage versus
Current
I
S
, SOURCE CURRENT (A)
T
J
= 25°C
V
GS
= 0 V
0.1
1
10
100
1000
1 10 100 1000
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
D
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
R
DS(on)
LIMIT
THERMAL LIMIT
PACKAGE LIMIT
V
GS
= 10 V
SINGLE PULSE
T
C
= 25°C
10 ms
100 ms
10 ms
dc
1 ms
0
10
20
30
40
50
60
70
80
25 50 75 100 125 150 1
AVALANCHE ENERGY (mJ)
T
J
, STARTING JUNCTION TEMPERATURE
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
I
D
= 23 A
0
400
800
1200
1600
0 20406080100
