12
LTC1285/LTC1288
Start Bit
The first “logical one” clocked into the D
IN
input after CS
goes low is the start bit. The start bit initiates the data
transfer. The LTC1288 will ignore all leading zeros which
precede this logical one. After the start bit is received, the
remaining bits of the input word will be clocked in. Further
inputs on the D
IN
pin are then ignored until the next CS
cycle.
Multiplexer (MUX) Address
The bits of the input word following the START bit assign
the MUX configuration for the requested conversion. For
a given channel selection, the converter will measure the
voltage between the two channels indicated by the “+”
and “–” signs in the selected row of the following tables.
In single-ended mode, all input channels are measured
with respect to GND.
APPLICATION INFORMATION
WUU
U
Data Transfer
The CLK synchronizes the data transfer with each bit
being transmitted on the falling CLK edge and captured
on the rising CLK edge in both transmitting and receiving
systems.
The LTC1285 does not require a configuration input word
and has no D
IN
pin. A falling CS initiates data transfer as
shown in the LTC1285 operating sequence. After CS falls
the second CLK pulse enables D
OUT
. After one null bit the
A/D conversion result is output on the D
OUT
line. Bringing
CS high resets the LTC1285 for the next data exchange.
The LTC1288 first receives input data and then transmits
back the A/D conversion result (half duplex). Because of
the half duplex operation, D
IN
and D
OUT
may be tied
together allowing transmission over just 3 wires: CS, CLK
and DATA (D
IN
/D
OUT
).
Data transfer is initiated by a falling chip select (CS) signal.
After CS falls the LTC1288 looks for a start bit. After the
start bit is received, the 3-bit input word is shifted into the
D
IN
input which configures the LTC1288 and starts the
conversion. After one null bit, the result of the conversion
is output on the D
OUT
line. At the end of the data exchange
CS should be brought high. This resets the LTC1288 in
preparation for the next data exchange.
D
IN
1 D
IN
2
D
OUT
1 D
OUT
2
CS
SHIFT MUX
ADDRESS IN
1 NULL BIT
SHIFT A/D CONVERSION
RESULT OUT
LTC1285/88 • AI01
the rising edge of the clock. The input data words are
defined as follows:
ODD/
SIGN
MSBFSTART
MUX
ADDRESS
MSB FIRST/
LSB FIRST
LTC1285/88 • AI02
SGL/
DIFF
LTC1288 Channel Selection
MUX ADDRESS
ODD/SIGN
0
1
0
1
CHANNEL #
0
+
+
–
1
+
–
+
GND
–
–
SINGLE-ENDED
MUX MODE
DIFFERENTIAL
MUX MODE
LTC1285/88 • AI03
SGL/DIFF
1
1
0
0
MSB First/LSB First (MSBF)
The output data of the LTC1288 is programmed for
MSB first or LSB first sequence using the MSBF bit.
When the MSBF bit is a logical one, data will appear on
the D
OUT
line in MSB first format. Logical zeros will be
filled in indefinitely following the last data bit. When the
MSBF bit is a logical zero, LSB first data will follow the
normal MSB first data on the D
OUT
line (see Operating
Sequence).
Input Data Word
The LTC1285 requires no D
IN
word. It is permanently
configured to have a single differential input. The conver-
sion result appears on the D
OUT
line. The data format is
MSB first followed by the LSB sequence. This provides
easy interface to MSB or LSB first serial ports. For MSB
first data the CS signal can be taken high after B0 (see
Figure 1). The LTC1288 clocks data into the D
IN
input on
