22
LTC1285/LTC1288
D
OUT
FROM 1288 STORED IN 8501 RAM
MSB
R2 B11 B10 B9 B8 B7 B6 B5 B4
LSB
R3 B3 B2 B1 B0 0 0 0 0
TYPICAL APPLICATIONS N
U
Interfacing to the Parallel Port of the INTEL 8051
Family
The Intel 8051 has been chosen to demonstrate the
interface between the LTC1288 and parallel port micro-
processors. Normally the CS, CLK and D
IN
signals would
be generated on 3 port lines and the D
OUT
signal read on
a 4th port line. This works very well. However, we will
demonstrate here an interface with the D
IN
and D
OUT
of the
LTC1288 tied together as described in the SERIAL INTER-
FACE section. This saves one wire.
The 8051 first sends the start bit and MUX address to the
LTC1288 over the data line connected to P1.2. Then P1.2
is reconfigured as an input (by writing to it a one) and the
8051 reads back the 12-bit A/D result over the same data
line.
LABEL MNEMONIC OPERAND COMMENTS
MOV A, #FFH D
IN
word for LTC1288
SETB P1.4 Make sure CS is high
CLR P1.4 CS goes low
MOV R4, #04 Load counter
LOOP 1 RLC A Rotate D
IN
bit into Carry
CLR P1.3 SCLK goes low
MOV P1.2, C Output D
IN
bit to LTC1288
SETB P1.3 SCLK goes high
DJNZ R4, LOOP 1 Next bit
MOV P1, #04 Bit 2 becomes an input
CLR P1.3 SCLK goes low
MOV R4, #09 Load counter
LOOP 2 MOV C, P1.2 Read data bit into Carry
RLC A Rotate data bit into Acc.
SETB P1.3 SCLK goes high
CLR P1.3 SCLK goes low
DJNZ R4, LOOP 2 Next bit
MOV R2, A Store MSBs in R2
CLR A Clear Acc.
MOV R4, #04 Load counter
LOOP 3 MOV C, P1.2 Read data bit into Carry
RLC A Rotate data bit into Acc.
SETB P1.3 SCLK goes high
CLR P1.3 SCLK goes low
DJNZ R4, LOOP 3 Next bit
MOV R4, #04 Load counter
LOOP 4 RRC A Rotate right into Acc.
DJNZ R4, LOOP 4 Next Rotate
MOV R3, A Store LSBs in R3
SETB P1.4 CS goes high
CS
CLK
D
OUT
D
IN
LTC1288
ANALOG
INPUTS
P1.4
P1.3
P1.2
8051
MUX ADDRESS
A/D RESULT
LTC1285/88 • TA01
CLK
MSBF BIT LATCHED
INTO LTC1288
8051 P1.2 OUTPUTS DATA
TO LTC1288
LTC1288 SENDS A/D RESULT
BACK TO 8051 P1.2
LTC1288 TAKES CONTROL OF DATA
LINE ON 4TH FALLING CLK
8051 P1.2 RECONFIGURED
AS IN INPUT AFTER THE 4TH RISING CLK
AND BEFORE THE 4TH FALLING CLK
MSBF B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
SGL/
DIFFSTART
DATA
(
D
IN
/D
OUT
)
LTC1285/88 • TA07
CS
ODD/
SIGN
