OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

NB3V8312CFAR2G

P1-P3P4-P6P7-P9P10-P11
NB3V8312C
http://onsemi.com
4
Table 3. ATTRIBUTES (Note 3)
Characteristics
Value
Internal Input Pullup (R
PU
) and Pulldown (R
PD
) Resistor
50 kW
Input Capacitance, C
IN
4 pF
Power Dissipation Capacitance, C
PD
(per Output) 20 pF
R
OUT
8 W
ESD Protection Human Body Model
Machine Model
> 1.5 kV
> 200 V
Moisture Sensitivity (Note 3) LQFP
QFN
Level 2
Level 1
Flammability Rating
Oxygen Index
UL−94 code V−0 A 1/8”
28 to 34
Transistor Count 464 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
3. For additional information, see Application Note AND8003/D.
Table 4. MAXIMUM RATINGS (Note 4)
Symbol Parameter Condition Rating Unit
V
DD
/
V
DDO
Positive Power Supply GND = 0 V 4.6 V
V
I
Input Voltage −0.5 v V
I
v V
DD
+ 0.5 V
T
stg
Storage Temperature Range −65 to +150 °C
q
JA
Thermal Resistance (Junction−to−Ambient)
(Note 5)
0 lfpm
500 lfpm
LQFP−32
LQFP−32
80
55
°C/W
°C/W
q
JC
Thermal Resistance (Junction−to−Case)
(Note 5)
Standard Board LQFP−32
LQFP−32
12−17 °C/W
q
JA
Thermal Resistance (Junction−to−Ambient)
(Note 5)
0 lfpm
500 lfpm
QFN*32
QFN*32
31
27
°C/W
q
JC
Thermal Resistance (Junction−to−Case)
(Note 5)
Standard
Board
QFN*32 12 °C/W
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
4. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and not valid simultaneously. If
stress limits are exceeded device functional operation is not implied, damage may occur and reliability may be affected.
5. JEDEC standard multilayer board − 2S2P (2 signal, 2 power).
NB3V8312C
http://onsemi.com
5
Table 5. LVCMOS/LVTTL DC CHARACTERISTICS (T
A
= −40°C to +85°C)
Symbol
Characteristics Conditions Min Typ Max Unit
V
IH
Input High Voltage
V
DD
= 3.465 V
2.0 V
DD
+
0.3
V
V
DD
= 2.625 V
1.7 V
DD
+
0.3
V
V
DD
= 2.0 V
0.65 x
V
DD
V
DD
+
0.3
V
V
IL
Input Low Voltage
V
DD
= 3.465 V −0.3 1.3 V
V
DD
= 2.625 V −0.3 0.7 V
V
DD
= 2.0 V
−0.3 0.35 x
V
DD
V
I
IH
Input High
Current
CLK
V
DD
= V
IN
= 3.465 V or 2.625 V or 2.0 V
150
mA
OE, CLK_EN 5
I
IL
Input Low
Current
CLK
V
DD
= 3.465 V or 2.625 V or 2.0 V, V
IN
= 0 V
−5
mA
OE, CLK_EN −150
V
OH
Output High Voltage (Note 6)
V
DDO
= 3.3 V ±5% 2.6
V
V
DDO
= 2.5 V ±5% 1.8
V
DDO
= 2.5 V ±5%; I
OH
= −1 mA 2.0
V
DDO
= 1.8 V ±0.2 V
V
DD
–
0.4
V
DDO
= 1.8 V ±0.2 V; I
OH
= −100 mA
V
DD
–
0.2
V
OL
Output Low Voltage (Note 6)
V
DDO
= 3. 3V ±5% 0.5
V
V
DDO
= 2.5 V ±5% 0.45
V
DDO
= 2.5 V ±5%; I
OL
= 1 mA 0.4
V
DDO
= 1.8 V ±0.2 V 0.35
V
DDO
= 1.8 V ±0.2 V; I
OL
= 100 mA
0.2
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
6. Outputs terminated 50 W to V
DDO
/2 unless otherwise specified. See Figure 7.
Table 6. POWER SUPPLY DC CHARACTERISTICS, (T
A
= −40°C to +85°C)
V
DD
(Core) V
DDO
(Outputs) Min Typ Max Unit
3.3 V ±5% 3.3 V ±5% 10 mA
3.3 V ±5% 2.5 V ±5% 10 mA
3.3 V ±5% 1.8 V ± 0.2V 10 mA
2.5 V ±5% 2.5 V ±5% 10 mA
2.5 V ±5% 1.8 V ± 0.2V 10 mA
1.8 V ± 0.2 V 1.8 V ± 0.2V 10 mA
NB3V8312C
http://onsemi.com
6
Table 7. AC CHARACTERISTICS (T
A
= −40°C to +85°C) (Note 7)
Symbol
Characteristic Min Typ Max Unit
f
MAX
Maximum Operating Frequency V
DD
/ V
DDO
3.3 V ±5% / 3.3 V ±5%
3.3 V ±5% / 2.5 V ±5%
3.3 V ±5% / 1.8 V ± 0.2 V
2.5 V ±5% / 2.5 V ±5%
2.5 V ±5% / 1.8 V ± 0.2 V
1.8 V ± 0.2 V / 1.8 V ± 0.2 V
250
250
200
250
200
200
MHz
t
pLH
Propagation Delay, Low to High; (Note 8) V
DD
/ V
DDO
3.3 V ±5% / 3.3 V ±5%
3.3 V ±5% / 2.5 V ±5%
3.3 V ±5% / 1.8 V ± 0.2 V
2.5 V ±5% / 2.5 V ±5%
2.5 V ±5% / 1.8 V ± 0.2 V
1.8 V ± 0.2 V / 1.8 V ± 0.2 V
0.9
1.0
1.0
1.3
1.3
2.4
2.2
2.3
3.0
3.1
3.5
4.2
ns
t
jit
Additive Phase Jitter, RMS; V
DD
/ V
DDO
f
C
= 100 MHz 3.3 V ±5% / 3.3 V ±5%
Integration Range: 12 kHz − 20 MHz 3.3 V ±5% / 2.5 V ±5%
See Figure 5 3.3 V ±5% / 1.8 V ± 0.2 V
2.5 V ±5% / 2.5 V ±5%
2.5 V ±5% / 1.8 V ± 0.2 V
1.8 V ± 0.2 V / 1.8 V ± 0.2 V
30
40
50
20
100
130
fs
t
sk(o)
Output−to−output skew; (Note 9); Figure 6 V
DD
/ V
DDO
3.3 V ±5% / 3.3 V ±5%
3.3 V ±5% / 2.5 V ±5%
3.3 V ±5% / 1.8 V ± 0.2 V
2.5 V ±5% / 2.5 V ±5%
2.5 V ±5% / 1.8 V ± 0.2 V
1.8 V ± 0.2 V / 1.8 V ± 0.2 V
125
135
145
150
150
140
ps
t
sk(pp)
Part−to−Part Skew; (Note 10) V
DD
/ V
DDO
3.3 V ±5% / 3.3 V ±5%
3.3 V ±5% / 2.5 V ±5%
3.3 V ±5% / 1.8 V ± 0.2 V
2.5 V ±5% / 2.5 V ±5%
2.5 V ±5% / 1.8 V ± 0.2 V
1.8 V ± 0.2 V / 1.8 V ± 0.2 V
250
250
250
250
250
250
ps
t
r
/t
f
Output rise and fall times V
DD
/ V
DDO
3.3 V ±5% / 3.3 V ±5%
3.3 V ±5% / 2.5 V ±5%
3.3 V ±5% / 1.8 V ± 0.2 V
2.5 V ±5% / 2.5 V ±5%
2.5 V ±5% / 1.8 V ± 0.2 V
1.8 V ± 0.2 V / 1.8 V ± 0.2 V
200
200
200
200
200
200
700
700
700
700
700
800
ps
ODC Output Duty Cycle (Note 11) V
DD
/ V
DDO
f ≤ 200 MHz, 3.3 V ±5% / 3.3 V ±5%
f ≤ 150 MHz, 3.3 V ±5% / 2.5 V ±5%
f ≤ 100 MHz, 3.3 V ±5% / 1.8 V ± 0.2 V
f ≤ 150 MHz, 2.5 V ±5% / 2.5 V ±5%
f ≤ 100 MHz, 2.5 V ±5% / 1.8 V ± 0.2 V
f ≤ 100 MHz, 1.8 V ± 0.2 V / 1.8 V ± 0.2 V
45
45
45
45
45
45
55
55
55
55
55
55
%
All parameters measured at f
MAX
unless noted otherwise.
7. Outputs loaded with 50 W to V
DDO
/2; see Figure 7. CLOCK input with 50% duty cycle; minimum input amplitude = 1.2 V at V
DD
= 3.3 V,
1.0 V at V
DD
= 2.5 V, V
DD
/2 at V
DD
= 1.8 V.
8. Measured from the V
DD
/2 of the input to V
DDO
/2 of the output.
9. Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DDO
/2.
10.Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions.
Using the same type of input on each device, the output is measured at V
DDO
/2.
11. Clock input with 50% duty cycles, rail−to−rail amplitude and t
r
/t
f
= 500 ps.
P1-P3P4-P6P7-P9P10-P11

NB3V8312CFAR2G

Mfr. #:
Buy NB3V8312CFAR2G
Manufacturer:
ON Semiconductor
Description:
Clock Buffer 1-TO-12 LVCMOS/LVTTL
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet