NB3V8312C
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7
Figure 5. Typical Phase Noise Plot at f
carrier
= 100 MHz at an Operating Voltage of 3.3 V, Room Temperature
NB3V8312C
Additive Phase Jitter @ 100 MHz
VDD = VDDO = 3.3 V
12 kHz to 20 MHz = 29.8 fs (typical)
Filter = 12 kHz − 20 MHz
Source RMS Jitter = 200.53 fs
Output RMS Jitter = 202.73 fs
RMS addititive jitter + RMS phase jitter of output
2
* RMS phase jitter of input
2
Ǹ
29.8 + 202.73 fs
2
* 200.53 fs
2
Ǹ
Output (DUT + Source)
Input Source
The above phase noise data was captured using Agilent
E5052A/B. The data displays the input phase noise and
output phase noise used to calculate the additive phase jitter
at a specified integration range. The RMS Phase Jitter
contributed by the device (integrated between 12 kHz and
20 MHz) is 29.8 fs.
The additive phase jitter performance of the fanout buffer
is highly dependent on the phase noise of the input source.
To obtain the most accurate additive phase noise
measurement, it is vital that the source phase noise be
notably lower than that of the DUT. If the phase noise of the
source is greater than the device under test output, the source
noise will dominate the additive phase jitter calculation and
lead to an artificially low result for the additive phase noise
measurement within the integration range. The Figure above
is a good example of the NB3V8312C source generator
phase noise having a significantly higher floor such that the
DUT output results in an additive phase jitter of 29.8 fs.
RMS addititive jitter + RMS phase jitter of output
2
* RMS phase jitter of input
2
Ǹ
29.8 + 202.73 fs
2
* 200.53 fs
2
Ǹ
