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SST39VF1601C-70-4C-EKE

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39
©2011 Silicon Storage Technology, Inc. DS-25018A 05/11
25
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
Data Sheet
A
Microchip Technology Company
Figure 14:Software ID Entry and Read
Figure 15:CFI Query Entry and Read
1380 F11.0
ADDRESS
T
IDA
DQ
15-0
WE#
SW0 SW1 SW2
555 2AA 555 0000 0001
OE#
CE#
Three-Byte Sequence for Software ID Entry
T
WP
T
WPH
T
AA
00BF
Device IDXX55XXAA XX90
Note: Device ID = 234BH for SST39VF1601C and 234AH for SST39VF1602C.
WP# must be held in proper logic state (V
IL
or V
IH
) 1µs after the command sequence.
X can V
IL
or V
IH
but no other value.
1380 F12.0
ADDRESS
T
IDA
DQ
15-0
WE#
SW0 SW1 SW2
555 2AA 555
OE#
CE#
Three-Byte Sequence for CFI Query Entry
T
WP
T
WPH
T
AA
XX55XXAA XX98
Note: WP# must be held in proper logic state (V
IL
or V
IH
) 1µs after the command sequence.
X can V
IL
or V
IH
but no other value.
©2011 Silicon Storage Technology, Inc. DS-25018A 05/11
26
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
Data Sheet
A
Microchip Technology Company
Figure 16:Software ID Exit/CFI Exit
Figure 17:SecIDEntry
1380 F13.0
ADDRESS
DQ
15-0
T
IDA
T
WP
T
WHP
WE#
SW0 SW1 SW2
555 2AA 555
THREE-BYTE SEQUENCE FOR
SOFTWARE ID EXIT AND RESET
OE#
CE#
XXAA XX55 XXF0
Note: WP# must be held in proper logic state (V
IL
or V
IH
) 1µs prior to and 1µs after the command sequence.
X can V
IL
or V
IH
but no other value.
1380 F20.0
ADDRESS A
MS-0
T
IDA
DQ
15-0
WE#
SW0 SW1 SW2
555 2AA 555
OE#
CE#
THREE-BYTE SEQUENCE FOR
CFI QUERY ENTRY
T
WP
T
WPH
T
AA
XX55XXAA XX88
Note: A
MS
= Most signifi-
cant address
A
MS
=A
19
WP# must be held in proper logic state (V
IL
or V
IH
) 1µs prior to and 1µs after the command sequence.
X can V
IL
or V
IH
but no other value.
©2011 Silicon Storage Technology, Inc. DS-25018A 05/11
27
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
Data Sheet
A
Microchip Technology Company
Figure 18:RST# Timing Diagram (When no internal operation is in progress)
Figure 19:RST# Timing Diagram (During Program or Erase operation)
Figure 20:AC Input/Output Reference Waveforms
1380 F29.0
RY/BY#
0V
RST#
CE#/OE#
T
RP
T
RHR
1380 F30.0
RY/BY#
CE#
OE#
T
RP
T
RY
T
BR
RST#
1380F14.0
REFERENCE POINTS OUTPUTINPUT
V
IT
V
IHT
V
ILT
V
OT
AC test inputs are driven at V
IHT
(0.9 V
DD
) for a logic ‘1’ and V
ILT
(0.1 V
DD
) for a logic ‘0’. Mea-
surement reference points for inputs and outputs are V
IT
(0.5 V
DD
) and V
OT
(0.5 V
DD
). Input rise
and fall times (10% 90%) are <5 ns.
Note: V
IT
-V
INPUT
Test
V
OT
-V
OUTPUT
Test
V
IHT
-V
INPUT
HIGH Test
V
ILT
-V
INPUT
LOW Test
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39

SST39VF1601C-70-4C-EKE

Mfr. #:
Buy SST39VF1601C-70-4C-EKE
Manufacturer:
Microchip Technology
Description:
NOR Flash 16M (1Mx16) 70ns Commercial Temp
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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