3948
DMOS FULL-BRIDGE
PWM MOTOR DRIVER
www.allegromicro.com
9
A3948SLB A3948SB
Terminal Name Terminal Description (SOIC) (DIP)
CP Reservoir capacitor (typically 0.22 µF) 1 24
CP1 & CP2 The charge pump capacitor (typically 0.22 µF) 2 & 3 1 & 2
PHASE Logic input for direction control (see also D15) 4 3
OSC Logic-level oscillator (square wave) input 5 4
GROUND Grounds 6, 7 5, 6, 7, 8*
LOGIC SUPPLY V
DD
, the low voltage (typically 5 V) supply 8 9
ENABLE Logic input for enable control (see also D14) 9 10
DATA Logic-level input for serial interface 10 11
CLOCK Logic input for serial port (data is entered on rising edge) 11 12
STROBE Logic input for serial port (active on rising edge) 12 13
REF V
REF
, the load current reference input volt. (see also D16) 13 14
MODE Logic input for PWM mode control (see also D17) 14 15
NO CONNECT No (Internal) Connection 15 —
OUT
A
One of two DMOS bridge outputs to the motor 16 16
SENSE Sense resistor 17 17
GROUND Grounds 18, 19 18, 19*
LOAD SUPPLY V
BB
, the high-current, 20 V to 50 V, motor supply 20 20
OUT
B
One of two DMOS bridge outputs to the motor 21 21
NO CONNECT No (Internal) connection 22 —
RANGE Logic Input for V
REF
range control (see also D16) 23 22
V
REG
Regulator decoupling capacitor (typically 0.22 µF) 24 23
* For the A3948SB DIP only, there is an indeterminate resistance between the substrate grounds (pins 6, 7, 18,
and 19) and the grounds at pins 5 and 8. Pins 5 and 8, and 6, 7, 18, or 19 must be connected together externally.
Terminal List
