AD9363 Data Sheet
Rev. D | Page 10 of 32
Table 5. VDD_INTERFACE = 2.5 V
Parameter Min Typ Max Unit Test Conditions/Comments
SLEEP MODE 150 μA Power applied, device disabled
ONE Rx CHANNEL, ONE Tx CHANNEL, DDR
LTE10
Single Port 6.5 mA 30.72 MHz data clock, CMOS
Dual Port 6.0 mA 15.36 MHz data clock, CMOS
LTE20
Dual Port 11.5 mA 30.72 MHz data clock, CMOS
TWO Rx CHANNELS, TWO Tx CHANNELS, DDR
LTE3
7.68 MHz data clock, CMOS
LTE10
Single Port 11.5 mA 61.44 MHz data clock, CMOS
Dual Port 10.0 mA 30.72 MHz data clock, CMOS
LTE20
Dual Port 20.0 mA 61.44 MHz data clock, CMOS
GSM
Dual Port 0.5 mA 1.08 MHz data clock, CMOS
WiMAX 8.75 MHz
Dual Port 7.3 mA 20 MHz data clock, CMOS
WiMAX 10 MHz
Single Port
TDD Rx 1.3 mA 22.4 MHz data clock, CMOS
TDD Tx 8.0 mA 22.4 MHz data clock, CMOS
FDD 8.7 mA 44.8 MHz data clock, CMOS
WiMAX 20 MHz
Dual Port
44.8 MHz data clock, CMOS