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ADALM-PLUTO

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33
AD9363 Data Sheet
Rev. D | Page 6 of 32
Parameter
1
Symbol Min Typ Max Unit Test Conditions/Comments
Receiver Differential Input
Impedance
100 Ω
Logic Outputs
Output Voltage High 1375 mV
Output Voltage Low 1025 mV
Output Differential
Voltage
150 mV Programmable in 75 mV steps
Output Offset Voltage 1200 mV
GENERAL-PURPOSE OUTPUTS
Output Voltage High VDD_GPO × 0.8 VDD_GPO V
Output Voltage Low 0 VDD_GPO × 0.2 V
Output Current
10
mA
SPI TIMING VDD_INTERFACE = 1.8 V
SPI_CLK
Period t
CP
20 ns
Pulse Width t
MP
9 ns
SPI_EN
Setup to First
SPI_CLK Rising Edge
t
SC
1 ns
Last SPI_CLK Falling Edge to
SPI_ENB Hold
t
HC
0 ns
SPI_DI
Data Input Setup to
SPI_CLK
t
S
2 ns
Data Input Hold to
SPI_CLK
t
H
1 ns
SPI_CLK Rising Edge to
Output Data Delay
4-Wire Mode t
CO
3 8 ns
3-Wire Mode t
CO
3 8 ns
Bus Turnaround Time, Read
(Master)
t
HZM
t
H
t
CO (MAX)
ns After baseband processors
(BBP) drives the last address bit
Bus Turnaround Time, Read
(Slave)
t
HZS
0 t
CO (MAX)
ns After AD9363 drives the last
data bit
DIGITAL DATA TIMING (CMOS),
VDD_INTERFACE = 1.8 V
DATA_CLK_x Clock Period t
CP
16.276 ns 61.44 MHz
DATA_CLK_x and FB_CLK_x
Pulse Width
t
MP
45% of t
CP
55% of t
CP
ns
Tx Data TX_FRAME_x, P0_Dx, and
P1_Dx
Setup to FB_CLK_x t
STX
1 ns
Hold to FB_CLK_x t
HTX
0 ns
DATA_CLK_x to Data Bus
Output Delay
t
DDRX
0
1.5
ns
DATA_CLK_x to
RX_FRAME_x Delay
t
DDDV
0 1.0 ns
Pulse Width
ENABLE
t
ENPW
t
CP
ns
TXNRX t
TXNRXPW
t
CP
ns FDD independent enable state
machine (ENSM) mode
TXNRX Setup to ENABLE t
TXNRXSU
0 ns TDD ENSM mode
Bus Turnaround Time TDD mode
Before Rx t
RPRE
2 × t
CP
ns
After Rx t
RPST
2 × t
CP
ns
Capacitive Load 3 pF
Capacitive Input 3 pF
Data Sheet AD9363
Rev. D | Page 7 of 32
Parameter
1
Symbol Min Typ Max Unit Test Conditions/Comments
DIGITAL DATA TIMING (CMOS),
VDD_INTERFACE = 2.5 V
DATA_CLK_x Clock Period t
CP
16.276 ns 61.44 MHz
DATA_CLK_x and FB_CLK_x
Pulse Width
t
MP
45% of t
CP
55% of t
CP
ns
Tx Data TX_FRAME_x, P0_Dx, and P1_Dx
Setup to FB_CLK_x t
STX
1 ns
Hold to FB_CLK_x t
HTX
0 ns
DATA_CLK_x to Data Bus
Output Delay
t
DDRX
0.25 1.25 ns
DATA_CLK_x to
RX_FRAME_x Delay
t
DDDV
0.25 1.25 ns
Pulse Width
ENABLE t
ENPW
t
CP
ns
TXNRX t
TXNRXPW
t
CP
ns FDD independent ENSM mode
TXNRX Setup to ENABLE t
TXNRXSU
0 ns TDD ENSM mode
Bus Turnaround Time TDD mode
Before Rx t
RPRE
2 × t
CP
ns
After Rx t
RPST
2 × t
CP
ns
Capacitive Load 3 pF
Capacitive Input 3 pF
DIGITAL DATA TIMING (LVDS)
DATA_CLK_x Clock Period t
CP
4.069 ns 245.76 MHz
DATA_CLK_x and FB_CLK_x
Pulse Width
t
MP
45% of t
CP
55% of t
CP
ns
Tx Data TX_FRAME_x and TX_Dx
Setup to FB_CLK_x t
STX
1 ns
Hold to FB_CLK_x t
HTX
0 ns
DATA_CLK_x to Data Bus
Output Delay
t
DDRX
0 1.5 ns
DATA_CLK_x to
RX_FRAME_x Delay
t
DDDV
0 1.0 ns
Pulse Width
ENABLE t
ENPW
t
CP
ns
TXNRX
t
TXNRXPW
t
CP
ns
FDD independent ENSM mode
TXNRX Setup to ENABLE t
TXNRXSU
0 ns TDD ENSM mode
Bus Turnaround Time
Before Rx t
RPRE
2 × t
CP
ns
After Rx t
RPST
2 × t
CP
ns
Capacitive Load 3 pF
Capacitive Input 3 pF
SUPPLY CHARACTERISTICS
1.3 V Main Supply 1.267 1.3 1.33 V
VDD_INTERFACE Supply
CMOS 1.2 2.5 V
LVDS 1.8 2.5 V
VDD_GPO Supply 1.3 3.3 3.465 V When unused, must be set to
1.3 V
Current Consumption
VDDx, Sleep Mode 180 µA Sum of all input currents
VDD_GPO 50 μA No load
1
When referencing a single function of a multifunction pin in the parameters, only the portion of the pin name that is relevant to the specification is listed. For full pin
names of multifunction pins, refer to the Pin Configuration and Function Descriptions section.
AD9363 Data Sheet
Rev. D | Page 8 of 32
CURRENT CONSUMPTION—VDD_INTERFACE
Table 3. VDD_INTERFACE = 1.2 V
Parameter Min Typ Max Unit Test Conditions/Comments
SLEEP MODE 45 μA Power applied, device disabled
ONE Rx CHANNEL, ONE Tx CHANNEL, DOUBLE
DATA RATE (DDR)
LTE10
Single Port 2.9 mA 30.72 MHz data clock, CMOS
Dual Port 2.7 mA 15.36 MHz data clock, CMOS
LTE20
Dual Port 5.2 mA 30.72 MHz data clock, CMOS
TWO Rx CHANNELS, TWO Tx CHANNELS, DDR
LTE3
Dual Port 1.3 mA 7.68 MHz data clock, CMOS
LTE10
Single Port 4.6 mA 61.44 MHz data clock, CMOS
Dual Port 5.0 mA 30.72 MHz data clock, CMOS
LTE20
Dual Port 8.2 mA 61.44 MHz data clock, CMOS
GSM
Dual Port 0.2 mA 1.08 MHz data clock, CMOS
WiMAX 8.75 MHz
Dual Port 3.3 mA 20 MHz data clock, CMOS
WiMAX 10 MHz
Single Port
TDD Rx 0.5 mA 22.4 MHz data clock, CMOS
TDD Tx 3.6 mA 22.4 MHz data clock, CMOS
FDD 3.8 mA 44.8 MHz data clock, CMOS
WiMAX 20 MHz
Dual Port
FDD 6.7 mA 44.8 MHz data clock, CMOS
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33

ADALM-PLUTO

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Buy ADALM-PLUTO
Manufacturer:
Analog Devices Inc.
Description:
AD9363 RF Transceiver Development Kit
Lifecycle:
New from this manufacturer.
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