1
X9258
Low Noise/Low Power/2-Wire Bus/256 Taps
Quad Digital Controlled Potentiometers
(XDCP™)
The X9258 integrates 4 digitally controlled potentiometers
(XDCP™) on a monolithic CMOS integrated circuit.
The digitally controlled potentiometer is implemented using
255 resistive elements in a series array. Between each
element are tap points connected to the wiper terminal
through switches. The position of the wiper on the array is
controlled by the user through the 2-wire bus interface. Each
potentiometer has associated with it a volatile Wiper Counter
Register (WCR) and 4 non-volatile Data Registers
(DR0:DR3) that can be directly written to and read by the
user. The contents of the WCR controls the position of the
wiper on the resistor array though the switches. Power-up
recalls the contents of DR0 to the WCR.
The XDCP™ can be used as a three-terminal potentiometer
or as a two-terminal variable resistor in a wide variety of
applications including control, parameter adjustments, and
signal processing.
Features
Four potentiometers in one package
256 resistor taps/potentiometer................. 0.4% resolution
2-wire serial interface
Wiper resistance, 40 typical @ V+ = 5V, V- = -5V
Four nonvolatile data registers for each potentiometer
Nonvolatile storage of wiper position
Standby current <5µA max (total package)
Power supplies
-V
CC
= 2.7V to 5.5V
- V+ = 2.7V to 5.5V
- V- = -2.7V to -5.5V
•100k, 50k total potentiometer resistance
High reliability
- Endurance: 100,000 data changes per bit per register
- Register data retention . . . . . . . . . . . . . . . . . . 100 years
24 Ld SOIC, 24 Ld TSSOP
Dual supply version of X9259
Pb-free (RoHS compliant)
Block Diagram
INTERFACE
AND
CONTROL
CIRCUITRY
SCL
SDA
A0
A1
A2
A3
R
0
R
1
R
2
R
3
WIPER
COUNTER
REGISTER
(WCR)
RESISTOR
ARRAY
POT 1
V
H1
/R
H1
V
L1
/R
L1
R
0
R
1
R
2
R
3
WIPER
COUNTER
REGISTER
(WCR)
V
H0
/R
H0
V
L0
/R
L0
DATA
8
V
W0
/R
W0
V
W1
/R
W1
R
0
R
1
R
2
R
3
RESISTOR
ARRAY
V
H2
/R
H2
V
L2
/R
L2
V
W2
/R
W2
R
0
R
1
R
2
R
3
RESISTOR
ARRAY
V
H3
/R
H3
V
L3
/R
L3
V
W3
/R
W3
WIPER
COUNTER
REGISTER
(WCR)
WIPER
COUNTER
REGISTER
(WCR)
POT 3
POT 2
WP
POT 0
V
CC
V
SS
V+
V-
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
| Copyright Intersil Americas Inc. 2005, 2006, 2011. All Rights Reserved
Intersil (and design) and XDCP are trademarks owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
Data Sheet FN8168.6December 15, 2011
2
FN8168.6
December 15, 2011
Ordering Information
PART NUMBER
(Note 2)
PART
MARKING
V
CC
LIMITS
(V)
POTENTIOMETER
ORGANIZATION
(k)
TEMPERATURE
RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
X9258US24Z (Note 1) X9258US Z 5 ±10 50 0 to +70 24 Ld SOIC (300 mil) M24.3
X9258US24IZ (Note 1) X9258US ZI -40 to +85 24 Ld SOIC (300 mil) M24.3
X9258UV24IZ X9258UV ZI -40 to +85 24 Ld TSSOP (4.4mm) MDP0044
X9258TS24Z X9258TS Z 100 0 to +70 24 Ld SOIC (300 mil) M24.3
X9258TS24IZ (Note 1) X9258TS ZI -40 to +85 24 Ld SOIC (300 mil) M24.3
X9258US24Z-2.7 (Note 1) X9258US ZF 2.7 to 5.5 50 0 to +70 24 Ld SOIC (300 mil) M24.3
X9258US24IZ-2.7 (Note 1) X9258US ZG -40 to +85 24 Ld SOIC (300 mil) M24.3
X9258UV24IZ-2.7 X9258UV ZG -40 to +85 24 Ld TSSOP (4.4mm) MDP0044
X9258TS24Z-2.7 (Note 1) X9258TS ZF 100 0 to +70 24 Ld SOIC (300 mil) M24.3
X9258TS24IZ-2.7 (Note 1) X9258TS ZG -40 to +85 24 Ld SOIC (300 mil) M24.3
X9258TV24IZ-2.7 X9258TV ZG -40 to +85 24 Ld TSSOP (4.4mm) MDP0044
X9258TV24Z-2.7 X9258TV ZF 0 to +70 24 Ld TSSOP (4.4mm) MDP0044
NOTES:
1. Add “T*” suffix for tape and reel. Please refer to TB347
for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for X9258
. For more information on MSL please see tech brief TB363.
X9258
3
FN8168.6
December 15, 2011
Pinout
X9258
(24 LD SOIC, TSSOP)
TOP VIEW
Pin Descriptions
Host Interface Pins
SERIAL CLOCK (SCL)
The SCL input is used to clock data into and out of the X9258.
SERIAL DATA (SDA)
SDA is a bidirectional pin used to transfer data into and out of
the device. It is an open drain output and may be wire-ORed
with any number of open drain or open collector outputs. An
open drain output requires the use of a pull-up resistor. For
selecting typical values, refer to “Guidelines for Calculating
Typical Values of Bus Pull-Up Resistors” on page 10.
DEVICE ADDRESS (A
0
- A
3
)
The Address inputs are used to set the least significant 4 bits
of the 8-bit slave address. A match in the slave address
serial data stream must be made with the address input in
order to initiate communication with the X9258. A maximum
of 16 devices may occupy the 2-wire serial bus.
Potentiometer Pins
V
H
/R
H
(V
H0
/R
H0
- V
H3
/R
H3
), V
L
/R
L
(V
L0
/R
L0
- V
L3
/R
L3
)
The V
H
/R
H
and V
L
/R
L
inputs are equivalent to the terminal
connections on either end of a mechanical potentiometer.
V
W
/R
W
(V
W0
/R
W0
- V
W3
/R
W3
)
The wiper outputs are equivalent to the wiper output of a
mechanical potentiometer.
Hardware Write Protect Input (WP)
The WP pin when low prevents nonvolatile writes to the Data
Registers.
Analog Supplies V+, V-
The Analog Supplies V+, V- are the supply voltages for the
DCP analog section.
Pin Names
Principles Of Operation
The X9258 is a highly integrated microcircuit incorporating
four resistor arrays and their associated registers and
counters and the serial interface logic providing direct
communication between the host and the DCP
potentiometers.
Serial Interface (2-Wire)
The X9258 supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter and the receiving device as the receiver.
The device controlling the transfer is a master and the
device being controlled is the slave. The master will always
initiate data transfers and provide the clock for both transmit
and receive operations. Therefore, the X9258 will be
considered a slave device in all applications.
NC
A0
V
W3
/R
W3
V+
V
CC
V
L0
/R
L0
1
2
3
4
5
6
7
8
9
10
24
23
22
21
20
19
18
17
16
15
A3
SCL
V
L2
/R
L2
V
H2
/R
H2
V
W2
/R
W2
V–
V
SS
V
W1
/R
W1
V
H1
/R
H1
V
L1
/R
L1
X9258
V
H3
/R
H3
14
13
11
12
V
L3
/R
L3
V
H0
/R
H0
V
W0
/R
W0
A2
A1
SDA
WP
SYMBOL DESCRIPTION
SCL Serial Clock
SDA Serial Data
A0 thru A3 Device Address
V
H0
/R
H0
thru V
H3
/R
H3
,
V
L0
/R
L0
thru V
L3
/R
L3
Potentiometer Pins
(terminal equivalent)
V
W0
/R
W0
thru V
W3
/R
W3
Potentiometers Pins
(wiper equivalent)
WP
Hardware Write Protection
V+, V- Analog Supplies
V
CC
System Supply Voltage
V
SS
System Ground
NC No Connection (Allowed)
X9258

X9258TS24IZ-2.7

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Digital Potentiometer ICs X9258TS24IZ-2 7 IIC 100K QD 256 TAPS
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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