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EVB-USB2250

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P43
USB2250/50i/51/51i
DS00002005A-page 13 2009 - 2015 Microchip Technology Inc.
SD Command SD_CMD 20 I/O12PU This is a bi-directional signal that connects to
the CMD signal of the SD/MMC device and has
a weak internal pull-up resistor.
SD Write
Protected
SD_WP 105 I/O12 Designates as the Secure Digital card
mechanical write detect pin.
SD Card Detect SD_nCD 32 I/O12 Designates as the Secure Digital card detection
pin.
USB INTERFACE
USB Bus Data USB+
USB-
7
8
I/O-U These pins connect to the USB bus data
signals.
USB Transceiver
Bias
RBIAS 127 I-R A 12.0 k, ±1.0% resistor is attached from VSS
to this pin in order to set the transceiver's
internal bias currents.
24 MHz Crystal
Input (External
Clock Input)
XTAL1
(CLKIN)
124 ICLKx This pin can be connected to one terminal of the
crystal or it can be connected to an external
24/48 MHz clock when a crystal is not used.
The MA[1:0] pins will be sampled while
RESET_N is asserted, and the value will be
latched upon RESET_N negation. This will
determine the clock source and value.
24 MHz Crystal
Output
XTAL2 123 OCLKx This is the other terminal of the crystal, or it is
left open when an external clock source is used
to drive XTAL1(CLKIN). It may not be used to
drive any external circuitry other than the crystal
circuit.
MEMORY / IO INTERFACE
Memory
Data Bus
MD[7:0] 33
29
30
31
34
35
36
37
I/O12PU These signals are used to transfer data between
the internal CPU and the external program
memory and have weak internal pull-up
resistors.
TABLE 5-1: USB2250/50I/51/51I 128-PIN VTQFP PIN DESCRIPTIONS (CONTINUED)
Name Symbol
128-Pin
VTQFP
Buffer
Type
Description
2009 - 2015 Microchip Technology Inc. DS00002005A-page 14
USB2250/50i/51/51i
Memory
Address Bus
MA16 28 O12 These signals address memory locations within
the external memory.
MA[15:2] 2
4
107
1
113
24
111
109
106
108
110
112
114
116
O12 These signals address memory locations within
the external memory.
MA[1:0] /
CLK_
SEL[1:0]
25
27
O12 MA[1:0]: These signals address memory
locations within the external memory.
I/O12PD CLK_SEL[1:0]: During RESET_N assertion,
these pins will select the operating frequency of
the external clock, and the corresponding weak
pull-down resistors are enabled.
When RESET_N is negated, the value on these
pins will be latched internally and these pins will
revert to MA[1:0] functionality; the internal pull-
downs will be disabled.
CLK_SEL[1:0] = '00'. 24 MHz
CLK_SEL[1:0] = '01'. RESERVED
CLK_SEL[1:0] = '10'. RESERVED
CLK_SEL[1:0] = '11'. 48 MHz
If the latched value is '1', the corresponding MA
pin is tri-stated when the chip is in power down
state.
If the latched value is '0', the corresponding MA
pin will function identically to MA[15:3] pins at all
times (other than during RESET_N assertion).
Memory Write
Strobe
nMWR 3 O12 This pin is the active low program Memory Write
strobe signal.
Memory Read
Strobe
nMRD 115 O12 This pin is the active low program Memory Read
strobe signal.
Memory Chip
Enable
nMCE 26 O12 This pin is the active low program Memory Chip
Enable strobe signal.
This signal is asserted when any external
access is being done by the processor.
This signal is held to the logic 'high' while
RESET_N is asserted.
TABLE 5-1: USB2250/50I/51/51I 128-PIN VTQFP PIN DESCRIPTIONS (CONTINUED)
Name Symbol
128-Pin
VTQFP
Buffer
Type
Description
USB2250/50i/51/51i
DS00002005A-page 15 2009 - 2015 Microchip Technology Inc.
MISC
General Purpose
Input/Output
LED 120 I/O12 LED: It can be used as an LED output.
VBUS_DET 121 I/O12 VBUS is a 3.3 volt input. A resistor divider must
be used if connecting to 5 volts of USB power.
SCL /
xD_ID
118 O12 SCL: This is the clock output when used with an
external EEPROM.
I/O12 xD_ID: This is the xD-Picture Card detection pin
only applicable to USB2250/USB2250i.
SDA 5 I/O12 SDA: This is the data pin when used with an
external serial EEPROM.
CRD_PWR0 14 I/O12 CRD_PWR: Card power drive of 3.3 V at either
100 mA or 200 mA.
I/O200
CRD_PWR1 78 I/O12 CRD_PWR: Card power drive of 3.3 V at either
100 mA or 200 mA.
I/O200
CRD_PWR2 76 I/O200 CRD_PWR: Card power drive of 3.3 V at either
100 mA or 200 mA.
Requirement: This must be the only FET used
to power SM devices. Failure to do this will
violate SM voltage specification on SM device
pins.
CRD_PWR3 16 I/O200 CRD_PWR: Card power drive of 3.3 V at either
100 mA or 200 mA.
Requirement: This must be the only FET used
to power SM devices. Failure to do this will
violate SM voltage specification on SM device
pins.
RESET Input RESET_N 64 IS This active low signal is used by the system to
reset the chip. The active low pulse should be
at least 1s wide.
TEST Input TEST 103 I Tie this pin to ground for normal operation.
Regulator Enable REG_EN 6 IPU This signal is used to enable the internal
1.8 V regulator.
DIGITAL POWER, and GROUND
1.8 V Digital Core
Power
VDD18 49 If the internal regulator is enabled, then this pin
must have a 1.0
F (or greater) ±20% (ESR
<0.1 ) capacitor to VSS.
1.8 V PLL Power VDD18PLL 125 If the internal regulator is enabled, then this pin
must have a 1.0
F (or greater) ±20% (ESR
<0.1 ) capacitor to VSS.
3.3 V Power and
Voltage Regulator
Input
VDD33 15
50
65
77
104
128
If the internal regulator is enabled, pins 50 and
128 each require an external bypass capacitor
of 4.7
F minimum.
TABLE 5-1: USB2250/50I/51/51I 128-PIN VTQFP PIN DESCRIPTIONS (CONTINUED)
Name Symbol
128-Pin
VTQFP
Buffer
Type
Description
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P43

EVB-USB2250

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Buy EVB-USB2250
Manufacturer:
Microchip Technology
Description:
Interface Development Tools USB2250 UltFastHiSpd Customer Eval Brd
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