6.42
11
High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges
IDT70V3599/89S
AC Electrical Characteristics Over the Operating Temperature Range
(Read and Write Cycle Timing)
(2,3)
(VDD = 3.3V ± 150mV)
NOTES:
1. The Pipelined output parameters (t
CYC2, tCD2) apply to either or both left and right ports when FT/PIPEX = VIH. Flow-through parameters (tCYC1, tCD1) apply when
FT/PIPE = V
IL for that port.
2. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE) and FT/PIPE. FT/PIPE should be treated as a
DC signal, i.e. steady state during operation.
3. These values are valid for either level of V
DDQ (3.3V/2.5V). See page 5 for details on selecting the desired operating voltage levels for each port.
70V3599/89S166
Com'l Only
70V3599/89S133
Com'l
& Ind
Symbol Parameter Min. Max. Min. Max. Unit
t
CYC1
Clock Cycle Time (Flow-Through)
(1)
20
____
25
____
ns
t
CYC2
Clock Cycle Time (Pipelined)
(1)
6
____
7.5
____
ns
t
CH1
Clock High Time (Flow-Through)
(1)
6
____
7
____
ns
t
CL1
Clock Low Time (Flow-Through)
(1)
6
____
7
____
ns
t
CH2
Clock High Time (Pipelined)
(2)
2.1
____
2.6
____
ns
t
CL2
Clock Low Time (Pipelined)
(1)
2.1
____
2.6
____
ns
t
SA
Address Setup Time 1.7
____
1.8
____
ns
t
HA
Address Hold Time 0.5
____
0.5
____
ns
t
SC
Chip Enable Setup Time 1.7
____
1.8
____
ns
t
HC
Chip Enable Hold Time 0.5
____
0.5
____
ns
t
SB
Byte Enable Setup Time 1.7
____
1.8
____
ns
t
HB
Byte Enable Hold Time 0.5
____
0.5
____
ns
t
SW
R/W Setup Time 1.7
____
1.8
____
ns
t
HW
R/W Hold Time 0.5
____
0.5
____
ns
t
SD
Input Data Setup Time 1.7
____
1.8
____
ns
t
HD
Input Data Hold Time 0.5
____
0.5
____
ns
t
SAD
ADS Setup Time
1.7
____
1.8
____
ns
t
HAD
ADS Hold Time
0.5
____
0.5
____
ns
t
SCN
CNTEN Setup Time
1.7
____
1.8
____
ns
t
HCN
CNTEN Hold Time
0.5
____
0.5
____
ns
t
SRPT
REPEAT Setup Time
1.7
____
1.8
____
ns
t
HRPT
REPEAT Hold Time
0.5
____
0.5
____
ns
t
OE
Output Enable to Data Valid
____
4.0
____
4.2 ns
t
OLZ
Output Enable to Output Low-Z 1
____
1
____
ns
t
OHZ
Output Enable to Output High-Z 1 3.6 1 4.2 ns
t
CD1
Clock to Data Valid (Flow-Through)
(1)
____
12
____
15 ns
t
CD2
Clock to Data Valid (Pipelined)
(1)
____
3.6
____
4.2 ns
t
DC
Data Output Hold After Clock High 1
____
1
____
ns
t
CKHZ
Clock High to Output High-Z 1 3 1 3 ns
t
CKLZ
Clock High to Output Low-Z 1
____
1
____
ns
Port-to-Port Delay
t
CO
Clock-to-Clock Offset 5
____
6
____
ns
5617 tbl 11
