6.42
19
High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges
IDT70V3599/89S
Functional Description
The IDT70V3599/89 provides a true synchronous Dual-Port Static
RAM interface. Registered inputs provide minimal set-up and hold times
on address, data, and all critical control inputs. All internal registers are
clocked on the rising edge of the clock signal, however, the self-timed
internal write pulse is independent of the LOW to HIGH transition of the clock
signal.
An asynchronous output enable is provided to ease asyn-
chronous bus interfacing. Counter enable inputs are also provided to stall
the operation of the address counters for fast interleaved
memory applications.
A HIGH on CE0 or a LOW on CE1 for one clock cycle will power down
the internal circuitry to reduce static power consumption. Multiple chip
enables allow easier banking of multiple IDT70V3599/89s for depth
expansion configurations. Two cycles are required with CE0 LOW and
CE1 HIGH to re-activate the outputs.
5617 drw 20
IDT70V3599/89
CE
0
CE
1
CE
1
CE
0
CE
0
CE
1
A
17
/A
16
(1)
CE
1
CE
0
V
DD
V
DD
IDT70V3599/89
IDT70V3599/89
IDT70V3599/89
Control Inputs
Control Inputs
Control Inputs
Control Inputs
BE,
R/W,
OE,
CLK,
ADS,
R EPEAT,
CNTEN
Depth and Width Expansion
The IDT70V3599/89 features dual chip enables (refer to Truth
Table I) in order to facilitate rapid and simple depth expansion with no
requirements for external logic. Figure 4 illustrates how to control the
various chip enables in order to expand two devices in depth.
The IDT70V3599/89 can also be used in applications requiring
expanded width, as indicated in Figure 4. Through combining the control
signals, the devices can be grouped as necessary to accommodate
applications needing 72-bits or wider.
Figure 4. Depth and Width Expansion with IDT70V3599/89
NOTE:
1. A
17 is for IDT70V3599, A16 is for IDT70V3589.
