6.42
18
High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges
IDT70V3599/89S
ADDRESS
An
D0
tCH2 tCL2
tCYC2
QLAST
QLAST+1
LAST ADS LOAD
CLK
DATA
IN
R/
W
REPEAT
5617 drw 19
INTERNAL
(3)
ADDRESS
ADS
CNTEN
tSRPT
tHRPT
tSD
tHD
tSW tHW
EXECUTE
REPEAT
WRITE
LAST ADS
ADDRESS
READ
LAST ADS
ADDRESS
READ
LAST ADS
ADDRESS + 1
READ
ADDRESS n
Qn
An + 1
An + 2
READ
ADDRESS n+1
DATA
OUT
tSA tHA
LAST ADS +1
An An + 1
(4)
(5)
(6)
Ax
tSAD tHAD
tSCN tHCN
Timing Waveform of Write with Address Counter Advance
(Flow-through or Pipelined Inputs)
(1)
Timing Waveform of Counter Repeat
(2)
NOTES:
1. CE
0, BEn, and R/W = VIL; CE1 and REPEAT = VIH.
2.
CE
0, BEn = VIL; CE1 = VIH.
3. The "Internal Address" is equal to the "External Address" when ADS = V
IL and equals the counter output when ADS = VIH.
4. Addresses do not have to be accessed sequentially since ADS = V
IL constantly loads the address on the rising edge of the CLK; numbers are for reference
use only.
5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
6. No dead cycle exists during REPEAT operation. A READ or WRITE cycle may be coincidental with the counter REPEAT cycle: Address loaded by last valid
ADS load will be accessed. Extra cycles are shown here simply for clarification. For more information on REPEAT function refer to Truth Table II.
7. CNTEN = V
IL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’Address is
written to during this cycle.
ADDRESS
An
CLK
DATA
IN
Dn
Dn + 1
Dn + 1 Dn + 2
ADS
CNTEN
t
CH2
t
CL2
t
CYC2
5617 drw 18
INTERNAL
(3)
ADDRESS
An
(7)
An + 1
An + 2
An + 3
An + 4
Dn + 3
Dn + 4
t
SA
t
HA
t
SAD
t
HAD
WRITE
COUNTER HOLD
WRITE WITH COUNTER
WRITE
EXTERNAL
ADDRESS
WRITE
WITH COUNTER
t
SD
t
HD
t
SCN
t
HCN
