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8312AYLFT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
1©2015 Integrated Device Technology, Inc December 11, 2015
General Description
The 8312 is a low skew, 1-to-12 LVCMOS/ LVTTL Fanout Buffer
and a member of the family of High Performance Clock Solutions
from IDT. The 8312 single-ended clock input accepts LVCMOS or
LVTTL input levels. The low impedance LVCMOS outputs are
designed to drive 50 series or parallel terminated transmission
lines. The effective fanout can be increased from 12 to 24 by
utilizing the ability of the outputs to drive two series terminated
lines.
The 8312 is characterized at full 3.3V, 2.5V, and 1.8V, mixed
3.3V/2.5V, 3.3V/1.8V and 2.5V/1.8V output operating supply
modes. Guaranteed output and part-to-part skew characteristics
along with the 1.8V output capabilities makes the 8312 ideal for
high performance, single ended applications that also require a
limited output voltage.
Features
• Twelve LVCMOS/LVTTL outputs
• CLK input supports the following input types: LVCMOS, LVTTL
• Maximum output frequency: 250MHz
• Output skew: 150ps (maximum)
• Supply modes:
Core/Output
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
2.5V/2.5V
2.5V/1.8V
1.8V/1.8V
• 0°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
8312
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
GND
V
DD
CLK_EN
CLK
GND
OE
V
DD
GND
Q4
V
DDO
Q5
GND
Q6
V
DDO
Q7
GND
Q11
V
DDO
Q10
GND
Q9
V
DDO
Q8
GND
V
DDO
Q1
GND
Q2
V
DDO
Q3
GND
Q0
Pin Assignment
D
LE
Q
Q[0:11]
CLK_EN
OE
CLK
Pullup
Pulldown
Pullup
12
Block Diagram
8312
Datasheet
Low Skew, 1-to-12 LVCMOS/LVTTL
Fanout Buffer
2©2015 Integrated Device Technology, Inc December 11, 2015
8312 Datasheet
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Number Name Type Description
1, 5, 8, 12, 16,
17, 21, 25, 29
GND Power Power supply ground.
2, 7 V
DD
Power Positive supply pins.
3 CLK_EN Input Pullup
Synchronous control for enabling and disabling clock outputs.
LVCMOS / LVTTL interface levels.
4 CLK Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels.
6 OE Input Pullup
Output enable. Controls enabling and disabling of outputs Q[0:11].
LVCMOS / LVTTL interface levels.
9, 11, 13, 15,
18, 20, 22, 24,
26, 28, 30, 32
Q11, Q10, Q9, Q8,
Q7, Q6, Q5, Q4,
Q3, Q2, Q1, Q0
Output Single-ended clock outputs. LVCMOS/LVTTL interface levels.
10, 14, 19, 23,
27, 31
V
DDO
Power Output supply pins.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4 pF
R
PULLUP
Input Pullup Resistor 51 k
R
PULLDOWN
Input Pulldown Resistor 51 k
C
PD
Power Dissipation Capacitance
(per output)
V
DDO
= 3.465V 19 pF
V
DDO
= 2.625V 18 pF
V
DDO
= 2V 16 pF
R
OUT
Output Impedance
V
DDO
= 3.3V ± 5% 7
V
DDO
= 2.5V ± 5% 7
V
DDO
= 1.8V ± 0.2V 10
3©2015 Integrated Device Technology, Inc December 11, 2015
8312 Datasheet
Function Tables
Table 3A. Output Enable and Clock Enable Function Table
Table 3B. Output Enable and Clock Enable Function Table
Inputs Outputs
OE CLK_EN Q [0:11]
0X Hi-Z
10 LOW
1 1 Follows CLK input
Inputs Outputs
OE CLK_EN CLK Q [0:11]
110LOW
111HIGH
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

8312AYLFT

Mfr. #:
Buy 8312AYLFT
Manufacturer:
IDT
Description:
Clock Buffer Low Skew,1:12 LVCMOS Fanout Buffer
Lifecycle:
New from this manufacturer.
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