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8312AYLFT
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
13
©2015 Inte
grated Device T
echnology
, Inc
December 1
1, 2015
8312 Data
sheet
Application Information
Recommendations f
or Unused
Input and Output Pins
Inputs:
L
VCMOS Co
ntrol
Pins:
All control
pins have
internal
pull-ups o
r pull-do
wns; addit
ional
resistance i
s not req
uired but
can be a
dded for
additional
protection.
A 1k
resistor
can be u
sed.
Outputs:
L
VCMOS Outputs:
All unus
ed L
VCMOS output ca
n be left floa
ting. There sho
uld be
no trace at
tached.
14
©2015 Inte
grated Device T
echnology
, Inc
December 1
1, 2015
8312 Data
sheet
Reliability Information
T
able 6.
JA
vs. Air Flo
w T
able f
or a 32 Lead LQFP
NO
TE: Most moder
n PCB design u
se multi-la
yered boards.
The data in the second row per
tains to most designs.
T
ransistor Count
The transistor count for 8312 is: 339
JA
vs. Air Flo
w
Linear Feet per Minute
02
0
0
5
0
0
Single-Layer PCB, JEDEC Standard Te
st Boards
67.8°C/W
55.9°C/W
50.1°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9°C/W
42.1°C/W
39.4
°C/W
15
©2015 Inte
grated Device T
echnology
, Inc
December 1
1, 2015
8312 Data
sheet
Package Outline and
Package Dimensions
P
ackage Outline - Y Suffix
for 32 Lead LQFP
T
able 7. P
acka
ge Dimensions for 32
Lead LQFP
Ref
erence Docu
ment: JEDEC Publication 95, MS-026
JEDEC V
ariation: ABC - HD
All Dimensions in Mill
imeters
Symbol
Minimu
m
Nominal
Maximum
N
32
A
1.60
A1
0.
05
0.10
0.15
A2
1.
35
1.40
1.45
b
0.30
0
.37
0.45
c
0.09
0.20
D & E
9.00 Basic
D1 & E1
7.00 Basic
D2 & E2
5.60 Ref
.
e
0.80 Basic
L
0.45
0
.60
0.75
0°
7°
ccc
0.10
N
32
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
8312AYLFT
Mfr. #:
Buy 8312AYLFT
Manufacturer:
IDT
Description:
Clock Buffer Low Skew,1:12 LVCMOS Fanout Buffer
Lifecycle:
New from this manufacturer.
Delivery:
DHL
FedEx
Ups
TNT
EMS
Payment:
T/T
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