ZSSC3131BA2T Datasheet ZSSC3131BA2R, ZSSC3131BE2T, ZSSC3131BE2R | P13-P15

ZSSC3131

Datasheet

January 25, 2016

2.3.4. Analog-to-Digital Converter

The A/D converter is implemented using full-differential switched-capacitor technique.

Programmable ADC resolutions are r

ADC

=<13, 14>bit.

The A/D conversion is integrating, inherently monotone, and insensitive to short and long term instability of the

clock frequency. The conversion time t

ADC

depends on the desired resolution and can be roughly calculated by

equation (1):













OSC

ADC

(1)

Where

ADC

Resolution of A/D conversion

OSC

Frequency of internal oscillator (refer to 1.3.1)

Refer to the ZSSC313x Bandwidth Calculation Sheet for a detailed calculation of sampling time and bandwidth.

The result of the A/D conversion is a relative counter result Z corresponding to the following equation:

)RS

(2Z

ADC_REF

ADC_DIFF

ADC

−⋅=

(2)

Where

ADC

Resolution of A/D conversion

ADC_DIFF

Differential ADC input voltage

ADC_REF

ADC reference voltage as selected by the BRREF bits in the EEPROM configuration word

CFGAPP (V

VBR_T

– V

VBR_B

if BRREF= 0) or (V

VDDA

– V

VSSA

if BRREF=1)*

RS Digital ADC Range Shift (RS = 1/16, 1/8, 1/4, 1/2) controlled by the ADCRS bits in the

EEPROM configuration word CFGAFE) Error! Bookmark not defined.

With the RS value, a sensor input signal can be shifted in the optimal input range of the ADC.

The condition required for ensuring the specified accuracy, stability, and non-linearity parameters of the analog

front-end is that the differential ADC input voltage V

ADC_DIFF

does not exceed the range of 10% to 90% of the ADC

reference voltage V

ADC_REF

. This requirement must be met for the whole temperature range and for all sensor

tolerances.

* Refer to the ZSSC313x Functional Description for more information on EEPROM contents.

ZSSC3131

Datasheet

January 25, 2016

Table 2.2 ADC Resolution versus Output Resolution and Sample Rate

ADC

Adjustment

Output Resolution

Sample Rate

Averaged Bandwidth

ADC

[bit]

Digital

[bit]

Analog

[bit]

OSC

=3MHz

[Hz]

OSC

=4MHz

[Hz]

OSC

=3MHz

[Hz]

OSC

=4MHz

[Hz]

13 13 12 345 460 130 172

14 14 12 178 237 67 89

1) Output resolution does not exceed ADC resolution. PGA gain should be such that the differential ADC input signal uses at least 50% of ADC input

range to ensure maximum achievable output resolution.

2) Refer to the ZSSC313x Bandwidth Calculation Sheet for a detailed calculation of sampling time and bandwidth.

2.4. Temperature Measurement

The ZSSC3131 supports acquiring temperature data needed for conditioning of the sensor signal using an

internal pn-junction temperature sensor. Refer to the ZSSC313x Functional Description for a detailed explanation

of temperature sensor adaptation and adjustment.

2.5. System Control and Conditioning Calculation

The system control supports the following tasks/features:

• Managing the startup sequence

• Controlling the measurement cycle regarding to the EEPROM-stored configuration data

• Sensor signal conditioning (calculation of the 16-bit correction for each measurement signal using the

EEPROM-stored conditioning coefficients and the ROM-based formulas)

• Processing communication requests received via the digital interfaces

• Performing failsafe tasks and message detected errors by setting diagnostic states

2.5.1. General Working Modes

ZSSC3131 supports three different working modes:

• Normal Operation Mode (NOM) – for continuous processing of signal conditioning

• Command Mode (CM) – for calibration and access to all internal registers

• Diagnostic Mode (DM) – for failure messages

2.5.2. Startup Phase

After power-on, the startup phase is processed, which includes

• Internal supply voltage settling including reset of the circuitry by the power-on reset block (POR).

Refer to the ZSSC313x High Voltage Protection Description for power-on/off thresholds.

Duration (beginning with V

VDDA

-V

VSSA

=0V): 500µs to 2ms; AOUT: high impedance.

• System start and configuration, EEPROM readout, and signature check.

Duration: ~200µs; AOUT: lower diagnostic range (LDR).

All timing values are roughly estimated for an oscillator frequency f

OSC

=3MHz and are proportional to that frequency.

ZSSC3131

Datasheet

January 25, 2016

• Processing the measurement cycle start routine.

Duration: 5x A/D conversion time; AOUT behavior depends on configured one-wire communication mode

(refer to section 2.6):

OWIANA or OWIDIS  AOUT: lower diagnostic range (LDR)

OWIWIN or OWIENA  AOUT: tri-state

If an error is detected during the startup phase, the Diagnostic Mode (DM) is activated and the analog output at

the AOUT pin remains in the lower diagnostic range.

After the startup phase, the continuous running measurement and sensor signal conditioning cycle is started, and

analog or digital output of the conditioned sensor signal is activated. If the one-wire communication mode

OWIWIN is selected, the OWI startup window expires before analog output is available.

2.5.3. Conditioning Calculation

The digitalized value for the bridge signal is processed with a conditioning formula to remove offset and

temperature dependency and to compensate nonlinearity up to 3

order. The result is a non-negative 15-bit value

for the measured bridge sensor signal in the range [0; 1). This value is available for readout via I²C™ or OWI

communication. For the analog output, the value is clipped to the programmed output limits.

Note: The extent of signal deviation that can be compensated by the conditioning calculation depends on the

specific sensor signal characteristics. For a rough estimation, assume the following: offset

compensation and gain correction are not limited. Note that resolution of the digitally gained signal is

determined by the ADC resolution in respect to the dynamic input range used. The temperature

correction includes first and second order terms and should be adequate for practically all relevant

cases. The non-linearity correction of the sensor signal is possible for second-order up to

approximately 30% FS regarding ideal fit and for third-order up to about 20% FS. Overall, the

conditioning formula applied is able to reduce the non-linearity of the sensor signal by a factor of 10.

2.6. Analog or Digital Output

The AOUT pin is used for analog output and for one-wire communication (OWI). The latter can be used for digital

readout of the conditioned sensor signal and for end-of-line sensor module calibration. The ZSSC3131 supports

different modes for the analog output in interaction with OWI communication as selected by EEPROM configura-

tion or by command:

• OWIENA: Analog output is deactivated; OWI readout of the signal data is enabled.

• OWIWIN: Analog output starts after the startup phase and after the OWI startup window if OWI

communication is not initiated; OWI communication for configuration or for end-of-line

calibration can be started during the OWI startup window (maximum ~500ms) by sending the

START_CM command.

• OWIANA: Analog output starts after the startup phase; OWI communication for configuration or for end-

of-line calibration can be started during the OWI startup window (maximum ~500ms) by

sending the START_CM command; for command transmission, the analog output driven at

the AOUT pin must be overwritten by the external communication master (AOUT drive

capability is current-limited).

• OWIDIS: Analog output starts after the startup phase; OWI readout of the signal data is disabled.

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ZSSC3131BA2T

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Sensor Interface Sensor Signal Conditoner

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ZSSC3131BA2T

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