Page 6 of 11
©2013 Peregrine Semiconductor Corp. All rights reserved. Document No. DOC-30414-2 │ UltraCMOS
®
RFIC Solutions
Product Specification
PE64909
Table 6. Serial Interface Timing Characteristics
V
DD
= 2.75V, -40°C < T
A
< +85°C, unless otherwise specified
Symbol Parameter Min Max Units
t
SCL
Serial clock period 38.4 ns
t
R
SCL, SDA, SEN rise time 6.5 ns
t
F
SCL, SDA, SEN fall time 6.5 ns
t
ESU
SEN rising edge to SCL rising edge 19.2 ns
t
EHD
SCL rising edge to SEN falling edge 19.2 ns
t
DSU
SDA valid to SCL rising edge 13.2 ns
t
DHD
SDA valid after SCL rising edge 13.2 ns
t
EOW
SEN falling edge to SEN rising edge 38.4 ns
t
SCLL
SCL low time 13.2 ns
t
SCLH
SCL high time 13.2 ns
b4 b3 b2 b1 b0
0 d3 d2 d1 d0
b5
STB
2
b7 b6
0
1
0
1
Table 5. 8-Bit Serial Programming Register Map
Figure 12. Recommended Bus Sharing
Serial Interface Operation and Sharing
The PE64909 is controlled by a three wire SPI-
compatible interface with enable active high. As shown in
Figure 11, the serial master initiates the start of a
telegram by driving the SEN (Serial Enable) line high.
Each bit of the 8-bit telegram (MSB first in) is clocked in
on the rising edge of SCL (Serial Clock), as shown in
Table 5 and Figure 11. Transitions on SDA (Serial Data)
are allowed on the falling edge of SCL. The DTC
activates the data on the falling edge of SEN. The DTC
does not count how many bits are clocked and only
maintains the last 8 bits it received.
More than 1 DTC can be controlled by one interface by
utilizing a dedicated enable (SEN) line for each DTC.
SDA, SCL, and V
DD
lines may be shared as shown in
Figure 12. Dedicated SEN lines act as a chip select such
that each DTC will only respond to serial transactions
intended for them. This makes each DTC change states
sequentially as they are programmed.
Alternatively, a dedicated SDA line with common SEN
can be used. This allows all DTCs to change states
simultaneously, but requires all DTCs to be programmed
even if the state is not changed.
Figure 11. Serial Interface Timing Diagram
MSB (first in) LSB (last in)
Notes: 1. These bits are reserved and must be written to 0 for proper operation
2. The DTC is active when low (set to 0) and in low-current stand-by
mode when high (set to 1)
SCL
SDA
V
DD
GND
DGND
RF-
RF+
SCL
SDA
V
DD
SEN
GND
DGND
RF-
RF+
SCL
SDA
V
DD
DTC 1
SEN
SEN2
SEN1
DTC 2
t
R
t
DHD
t
DSU
t
SCL
b1b7 b0
D
m-1
<7:0> D
m
<7:0>
b0
D
m-2
<7:0>
t
EOW
t
F
t
ESU
t
EHD
SEN
SCL
SDA
DTC Data
b2b3
b4b5b6
t
SCLH
t
SCLL
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