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EK64909-12

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Document No. DOC-30414-2 │ www.psemi.com ©2013 Peregrine Semiconductor Corp. All rights reserved.
Product Specification
PE64909
Equivalent Circuit Model Description
The DTC Equivalent Circuit Model includes all
parasitic elements and is accurate in both Series
and Shunt configurations, reflecting physical circuit
behavior accurately and providing very close
correlation to measured data. It can easily be used
in circuit simulation programs.
For V
P
and V
M
max operating limits, refer to
Table 3.
Table 7. Equivalent Circuit Model Parameters
Table 8. Equivalent Circuit Data
RF+ RF-
L
S
L
S
R
S
C
S
C
P2
C
P1
R
P1
R
P1
R
P2
R
P2
RFGND
V
M
V
P
Variable Equation (state = 0, 1, 2…15) Unit
C
S
0.127*state + 0.20 pF
R
S
20/(state+20/(state+0.7)) + 0.7
Ω
R
P1
10+4*state Ω
R
P2
40000+10*state^3 Ω
C
P1
-0.01*state + 0.40 pF
C
P2
0.0133*state + 0.45 pF
L
S
0.35 nH
State DTC Core Parasitic Elements
Hex Bin Dec
C
S
[pF]
R
S
[Ω]
C
P1
[pF]
C
P2
[pF]
R
P1
[Ω]
R
P2
[kΩ]
0x00 0000 0 0.20 1.40 0.40 0.45 10.0 40.0
0x01 0001 1 0.33 2.27 0.39 0.46 14.0 40.0
0x02 0010 2 0.45 2.83 0.38 0.48 18.0 40.1
0x03 0011 3 0.58 3.08 0.37 0.49 22.0 40.3
0x04 0100 4 0.71 3.12 0.36 0.50 26.0 40.6
0x05 0101 5 0.83 3.05 0.35 0.52 30.0 41.3
0x06 0110 6 0.96 2.93 0.34 0.53 34.0 42.2
0x07 0111 7 1.09 2.78 0.33 0.54 38.0 43.4
0x08 1000 8 1.21 2.64 0.32 0.56 42.0 45.1
0x09 1001 9 1.34 2.51 0.31 0.57 46.0 47.3
0x0A 1010 10 1.47 2.39 0.30 0.58 50.0 50.0
0x0B 1011 11 1.59 2.27 0.29 0.60 54.0 53.3
0x0C 1100 12 1.72 2.17 0.28 0.61 58.0 57.3
0x0D 1101 13 1.84 2.08 0.27 0.62 62.0 62.0
0x0E 1110 14 1.97 2.00 0.26 0.64 66.0 67.4
0x0F 1111 15 2.10 1.93 0.25 0.65 70.0 73.8
Figure 13. Equivalent Circuit Model Schematic
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
Page 8 of 11
©2013 Peregrine Semiconductor Corp. All rights reserved. Document No. DOC-30414-2 │ UltraCMOS
®
RFIC Solutions
Product Specification
PE64909
Series Operation
In Series configuration, the effective capacitance
between RF+ and RF- ports is represented by C
s
and tuning ratio as C
Smax
/C
Smin
.
Figure 17. Measured Series S
21
vs. Frequency
(major states)
Figure 16. Measured Series S
11
/S
22
(major states)
Configuration
C
min
(state 0)
C
max
(state 31)
Tuning
Ratio
Series (RF+ to RF-) 0.20 2.10 10.5:1
0.60 2.35 3.9:1 Shunt (RF+ to GND)
Effective
Capacitance
C
S
C
S
+ C
P1
When the DTC is used as a part of a reactive
network, impedance transformation may cause the
internal RF voltages (V
P
and V
M
in Figure 13) to
exceed peak operating RF voltage. The complete
RF circuit must be simulated using actual input
power and load conditions to ensure neither V
P
nor
V
M
exceeds 30 Vpk.
Figure 14. Effective Capacitance Diagram
Figure 15. Typical Capacitance vs. State
S
11
and S
21
for series configuration is illustrated in
Figures 16 and 17. S
21
includes mismatch and
dissipative losses and is not indicative of tuning
network loss. Equivalent Circuit Model can be used
for simulation of tuning network loss.
0 0.5 1 1.5 2 2.5 3
-40
-35
-30
-25
-20
-15
-10
-5
0
Frequency (GHz)
dB(S
21
)
C0
C1
C2
C4
C8
C15
Frequency(.3 - 3000 MHz)
S
11
C0
S
22
C0
S
11
C1
S
22
C1
S
11
C2
S
22
C2
S
11
C4
S
22
C4
S
11
C8
S
22
C8
S
11
C15
S
22
C15
Table 9. Effective Capacitance Summary
0.0
0.5
1.0
1.5
2.0
2.5
051015
Capacitance
State
Capacitance in Series
Configuration (Cs)
Capacitance in Shunt
Configuration (Cs+Cp1)
Shunt Configuration (looking into RF+ when RF- is
grounded) will have higher total capacitance at RF+
due to parallel combination of Cs with parasitic
capacitance C
P1
(C
S
+ C
P1
), as demonstrated in
Figure 15 and Table 9.
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
Page 9 of 11
Document No. DOC-30414-2 │ www.psemi.com ©2013 Peregrine Semiconductor Corp. All rights reserved.
Product Specification
PE64909
Figure 20. Evaluation Board Layout
Evaluation Board
The 101-0675 Evaluation Board (EVB) was designed
for accurate measurement of the DTC impedance
and loss. Two configurations are available: 1 Port
Shunt (J3) and 2 Port Shunt (J4, J5). Three
calibration standards are provided. The open (J2)
and short (J1) standards (104 ps delay) are used for
performing port extensions and accounting for
electrical length and transmission line loss. The Thru
(J9, J10) standard can be used to estimate PCB
transmission line losses for scalar de-embedding of
the 2 Port Series configuration (J4, J5).
The board consists of a 4 layer stack with 2 outer
layers made of Rogers 4350B (ε
r
= 3.48) and 2 inner
layers of FR4 (ε
r
= 4.80). The total thickness of this
board is 62 mils (1.57 mm). The inner layers provide
a ground plane for the transmission lines. Each
transmission line is designed using a coplanar
waveguide with ground plane (CPWG) model using a
trace width of 32 mils (0.813 mm), gap of 15 mils
(0.381 mm), and a metal thickness of 1.4 mils
(0.051 mm).
101-0675
Figure 19. Recommended Layout of Multiple DTCs
Figure 18. Recommended Schematic of
Multiple DTCs
Layout Recommendations
For optimal results, place a ground fill directly under
the DTC package on the PCB. Layout isolation is
desired between all control and RF lines. When
using the DTC in a shunt configuration, it is
important to make sure the RF-pin is solidly
grounded to a filled ground plane. Ground traces
should be as short as possible to minimize
inductance. A continuous ground plane is preferred
on the top layer of the PCB. When multiple DTCs
are used together, the physical distance between
them should be minimized and the connection
should be as wide as possible to minimize series
parasitic inductance.
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
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