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LIS3L02DQ
8.16 OUTY_H (2Bh)
When reading the register in “12 bit right justified” mode the most significant bits (7:4) are replaced with bit 3 (i.e. YD15-
YD12=YD11, YD11, YD11, YD11)
.
8.17 OUTZ_L (2Ch)
8.18 OUTZ_H (2Dh)
When reading the register in “12 bit right justified” mode the most significant bits (7:4) are replaced with bit 3 (i.e. ZD15-
ZD12=ZD11, ZD11, ZD11, ZD11)
.
8.19 THS_L (2Eh)
The registers THS_L and THS_H contain the upper and lower threshold that is valid for all three axes.
Each axis can be enabled/disabled for interrupt generation and upper/lower limits crossing can be used
for interrupt generation on a channel by channel basis
8.20 THS_H (2Fh)
YD15 YD14 YD13 YD12 YD11 YD10 YD9 YD8
YD15, YD8 Y axis acceleration data MSB
ZD7 ZD6 ZD5 ZD4 ZD3 ZD2 ZD1 ZD0
ZD7, ZD0 Z axis acceleration data LSB
ZD15 ZD14 ZD13 ZD12 ZD11 ZD10 ZD9 ZD8
ZD15, ZD8 Z axis acceleration data MSB
THS7 THS6 THS5 THS4 THS3 THS2 THS1 THS0
THS7, THS0 Inertial Wake Up Acceleration Threshold Lsb
THS15 THS14 THS13 THS12 THS11 THS10 THS9 THS8
THS15, THS8 Inertial Wake Up Acceleration Threshold Msb
