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410-251-B

P1-P3P4-P6P7-P9P10-P12
JTAG -SMT2™ Programming Module for Xilinx® FPGAs
Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.
Page 10 of 12
6 Absolute Maximum Ratings
Symbol
Parameter
Condition
Min
Max
Unit
Vdd
Operating supply voltage
-0.3
4.0
V
Vref
I/O reference/supply voltage
-0.3
6
V
VIO
Signal Voltage
-0.3
6
V
I
IK
,I
OK
TMS, TCK, TDI, TDO, GPIO0, GPIO1,
GPIO2
DC Input/Output Diode Current
VIO < -0.3V
-50
mA
VIO > 6V
+20
I
OUT
DC Output Current
±50
mA
T
STG
Storage Temperature
-10
+60
ºC
ESD
Human Body Model JESD22-A114
4000
V
Charge Device Model JESD22-C101
2000
V
7 DC Operating Characteristics
Symbol
Parameter
Min
Typ
Max
Unit
Vdd
Operating supply voltage
2.97
3.3
3.63
Volts
Vref
I/O reference/supply voltage
1.65
2.5/3.3
5.5
Volts
TDO, GPIO0,
GPIO1, GPIO2
Input High Voltage (V
IH
)
1.62
5.5
Volts
Input Low Voltage (V
IL
)
0
0.65
Volts
TMS, TCK, TDI,
GPIO0, GPIO1,
GPIO2
Output High (V
OH
)
0.85 x Vref
0.95 x Vref
Vref
Volts
Output Low (V
OL
)
0
0.05 x Vref
0.15 x Vref
Volts
T
A
Operating Temperature
-40
-85
ºC
JTAG -SMT2™ Programming Module for Xilinx® FPGAs
Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.
Page 11 of 12
8 AC Operating Characteristics
The JTAG-SMT2’s JTAG signals operate according to the timing diagram in Fig. 12. The SMT2 supports JTAG/TCK
frequencies from 30 MHz to 8 KHz at integer divisions of 30 MHz from 1 to 3750. Common frequencies include 30
MHz, 15 MHz, 10 Mhz, 7.5 MHz, and 6 MHz (see Table 2). The JTAG/TCK operating frequency can be set within the
Xilinx Tools. Note: Please refer to Xilinx’s iMPACT documentation for more information.
TDI
TCK
TDO
T
CKH
T
CKL
T
CK
T
CD_TDI
T
HD
T
SETUP
TMS
T
CD_TMS
9 Mounting to Host PCBs
The JTAG-SMT2 module has a moisture sensitivity level (MSL) of 3. It is suitable for reflow for up to 168 hours
without additional drying.
The factory finishes the JTAG-SMT2 signal pads with the ENIG process using 2u” gold over 150u” electroless nickel.
This makes the SMT2 compatible with most mounting and reflow processes (see Fig. 13). The binding force of the
solder is sufficient to hold the SMT2 firmly in place so mounting should require no additional adhesives.
Symbol
Parameter
Min
Max
T
CK
T
CK
period
30ns
125µs
T
CKH
, T
CKL
T
CLK
pulse width
15ns
62.5µs
T
CD_TMS
T
CLK
to TMS
-0.5ns
12.35ns
T
CD_TDI
T
CLK
to TDI
-0.5ns
8.15ns
T
SETUP
TDO Setup time
15.8ns
T
HD
TDO Hold time
0ns
Figure 12. Timing diagram.
Figure 12. Timing diagram.
Noteoajfojeafa
Note
Table 2. JTAG signal timing.
Note: these parameters are specified for Vref = 3.3V.
JTAG -SMT2™ Programming Module for Xilinx® FPGAs
Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.
Page 12 of 12
Limit time above
205°C to less
than 110s
10 Packaging
Digilent ships small quantities of less than 45 per order individually packaged in antistatic bags. Digilent will pack
and ship larger quantities in groups of 45 positioned in an antistatic bubble tray (see Fig. 14).
35cm
28cm
Figure 13. JTAG-SMT2 reflow temperature over time.
Figure 14. JTAG-SMT2 shipping arrangement.
P1-P3P4-P6P7-P9P10-P12

410-251-B

Mfr. #:
Buy 410-251-B
Manufacturer:
Digilent
Description:
Hardware Debuggers JTAG-SMT2, tray
Lifecycle:
New from this manufacturer.
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