10
COMMERCIAL TEMPERATURE RANGE
IDT7290820 5V TIME SLOT INTERCHANGE
DIGITAL SWITCH 2,048 x 2,048
TABLE 3 CONSTANT THROUGHPUT DELAY VALUE
TABLE 4 INTERNAL REGISTER AND ADDRESS MEMORY MAPPING
TABLE 2 VARIABLE THROUGHPUT DELAY VALUE
Delay for Variable Throughput Delay Mode
Input Rate (m – output channel number)
(n – input channel number)
m < n m = n, n+1, n+2 m > n+2
2.048 Mb/s 32 – (n-m) time-slots m-n + 32 time slots m-n time-slots
4.096 Mb/s 64 – (n-m) time-slots m-n + 64 time-slots m-n time slots
8.192 Mb/s 128 – (n-m) time-slots m-n + 128 time-slots m-n time-slots
Delay for Constant Throughput Delay Mode
Input Rate (m – output channel number)
(n – input channel number)
2.048 Mb/s 32 + (32 – n) + m time-slots
4.096 Mb/s 64 + (64 – n) + m time-slots
8.192 Mb/s 128 + (128 – n) + m time-slots
A7
(1)
A6 A5 A4 A3 A2 A1 A0 Location
00000000Control Register, CR
00000001Interface Mode Selection Register, IMS
00000010Frame Alignment Register, FAR
00000011Frame Input Offset Register 0, FOR0
00000100Frame Input Offset Register 1, FOR1
00000101Frame Input Offset Register 2, FOR2
00000110Frame Input Offset Register 3, FOR3
10000000Ch0
10000001Ch1
100......
10011110Ch30
10011111Ch31 (Note 2)
10100000Ch32
10100001Ch33
101......
10111110Ch62
10111111Ch63 (Note 3)
11000000Ch64
11000001Ch65
110......
11111110Ch126
11111111Ch127 (Note 4)
Notes:
1. Bit A7 must be high for access to data and connection memory positions. Bit A7 must be low for access to registers.
2. Channels 0 to 31 are used when serial interface is at 2.048 Mb/s mode
3. Channels 0 to 63 are used when serial interface is at 4.096 Mb/s mode.
4. Channels 0 to 127 are used when serial interface is at 8.192 Mb/s mode.
11
COMMERCIAL TEMPERATURE RANGE
IDT7290820 5V TIME SLOT INTERCHANGE
DIGITAL SWITCH 2,048 x 2,048
TABLE 6 CONTROL REGISTER (CR) BITS
TABLE 7 VALID ADDRESS LINES FOR DIFFERENT BIT RATES
TABLE 5 OUTPUT HIGH IMPEDANCE CONTROL
OE bit in Connection ODE pin OSB bit in IMS TX Output Driver
Memory Register Status
0 Don’t Care Don’t Care Per Channel
High-Impedance
1 0 0 High-Impedance
1 0 1 Enable
1 1 1 Enable
1 1 0 Enable
Read/Write Address: 00H,
Reset Value: 0000
H.
1514131211109876543210
0000000000MBPMSSTA3 STA2 STA1 STA0
Bit Name Description
15-6 Unused Must be zero for normal operation.
5 MBP When 1, the connection memory block programming feature is ready for the programming of Connection
(Memory Block Program) Memory high bits, bit 11 to bit 15. When 0, this feature is disabled.
4 MS When 0, connection memory is selected for read or write operations. When 1, the data memory is selected
(Memory Select) for read operations and connection memory is selected for write operations.
(No microprocessor write operation is allowed for the data memory).
3-0 STA3-0 The binary value expressed by these bits refers to the input or output data stream, which corresponds
(Stream Address Bits) to the subsection of memory made accessible for subsequent operations. (STA3 = MSB, STA0 = LSB)
Input/Output Valid Address Lines
Data Rate
2.048 Mb/s A4, A3, A2, A1, A0
4.096 Mb/s A5, A4, A3, A2, A1, A0
8.192 Mb/s A6, A5, A4, A3, A2, A1, A0
12
COMMERCIAL TEMPERATURE RANGE
IDT7290820 5V TIME SLOT INTERCHANGE
DIGITAL SWITCH 2,048 x 2,048
TABLE 8 INTERFACE MODE SELECTION (IMS) REGISTER BITS
TABLE 9 SERIAL DATA RATE SELECTION (16 INPUT x 16 OUTPUT)
DR1 DR0 Data Rate Selected Master Clock Required
0 0 2.048 Mb/s 4.096 MHz
0 1 4.096 Mb/s 8.192 MHz
1 0 8.192 Mb/s 16.384 MHz
1 1 Reserved Reserved
Read/Write Address: 01H,
Reset Value: 0000
H.
Bit Name Description
15-10 Unused Must be zero for normal operation.
9-5 BPD4-0 These bits carry the value to be loaded into the connection memory block whenever the memory block
(Block Programming Data) programming feature is activated. After the MBP bit in the control register is set to 1 and the BPE bit is
set to 1, the contents of the bits BPD4-0 are loaded into bit 15 and 11 of the connection memory. Bit 10 to
bit 0 of the connection memory are set to 0.
4 BPE A zero to one transition of this bit enables the memory block programming function. The BPE and
(Begin Block Programming BPD4-0 bits in the IMS register have to be defined in the same write operation. Once the BPE bit is set
Enable) HIGH, the device requires two frames to complete the block programming. After the programming function
has finished, the BPE bit returns to zero to indicate the operation is completed. When the BPE = 1, the BPE
or MBP can be set to 0 to ensure proper operation. When BPE = 1, the other bit in the IMS register
must not be changed for two frames to ensure proper operation.
3 OSB When ODE = 0 and OSB = 0, the output drivers of TX0 to TX15 are in high impedance mode. When
(Output Stand By) ODE= 0 and OSB = 1, the output driver of TX0 to TX15 function normally. When ODE = 1, TX0 to TX15
output drivers function normally.
2 SFE A zero to one transition in this bit starts the frame evaluation procedure. When the CFE bit in the FAR
(Start Frame Evaluation) register changes from zero to one, the evaluation procedure stops. To start another fame evaluation
cycle, set this bit to zero for at least one frame.
1-0 DR0-1 Input/Output data rate selection. See Table 9 for detailed programming.
(Data Rate Select)
1514131211109876543210
000000BPD4 BPD3 BPD2 BPD1 BPD0 BPE OSB SFE DR1 DR0

7290820JG

Mfr. #:
Manufacturer:
IDT
Description:
Digital Bus Switch ICs 2K X 2K TSI SWITCH
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union