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COMMERCIAL TEMPERATURE RANGE
IDT7290820 5V TIME SLOT INTERCHANGE
DIGITAL SWITCH 2,048 x 2,048
FUNCTIONAL DESCRIPTION
The IDT7290820 is capable of switching up to 2,048 x 2,048, 64 Kbit/s PCM
or N x 64 Kbit/s channel data. The device maintains frame integrity in data
applications and minimum throughput delay for voice applications on a per
channel basis.
The serial input streams of the IDT7290820 can have a bit rate of 2.048,
4.096 or 8.192 Mb/s and are arranged in 125µs wide frames, which contain
32, 64 or 128 channels respectively. The data rates on input and output streams
are identical.
In Processor Mode, the microprocessor can access input and output time-
slots on a per channel basis allowing for transfer of control and status information.
The IDT7290820 automatically identifies the polarity of the frame synchroniza-
tion input signal and configures the serial streams to either ST-BUS
®
or GCI
formats.
With the variety of different microprocessor interfaces, IDT7290820 has
provided an Input Mode pin (IM) to help integrate the device into different
microprocessor based environments: Non-multiplexed or Multiplexed. These
interfaces provide compatibility with multiplexed and Motorola non-multiplexed
buses. The device can also resolve different control signals eliminating the use
of glue logic necessary to convert the signals (R/W/WR, DS/RD, AS/ALE).
The frame offset calibration function allows users to measure the frame offset
delay using a frame evaluation pin (FE). The input offset delay can be
programmed for individual streams using internal frame input offset registers, see
Table 11.
The internal loopback allows the TX output data to be looped around to the
RX inputs for diagnostic purposes.
A functional Block Diagram of the IDT7290820 is shown in Figure 1.
DATA AND CONNECTION MEMORY
The received serial data is converted to parallel format by internal serial-
to-parallel converters and stored sequentially in the data memory. The 8KHz
input frame pulse (F0i) is used to generate channel and frame boundaries of
the input serial data. Depending on the interface mode select (IMS) register,
the usable data memory may be as large as 2,048 bytes.
Data to be output on the serial streams (TX0-15) may come from either the
data memory or connection memory. For data output from data memory
(connection mode), addresses in the connection memory are used. For data
to be output from connection memory, the connection memory control bits must
set the particular TX output in Processor Mode. One time-slot before the data
is to be output, data from either connection memory or data memory is read
internally. This allows enough time for memory access and parallel-to-serial
conversion.
CONNECTION AND PROCESSOR MODES
In the Connection Mode, the addresses of the input source data for all output
channels are stored in the connection memory. The connection memory is
mapped in such a way that each location corresponds to an output channel on
the output streams. For details on the use of the source address data (CAB and
SAB bits), see Table 13 and Table 14. Once the source address bits are
programmed by the microprocessor, the contents of the data memory at the
selected address are transferred to the parallel-to-serial converters and then
onto a TX output stream.
By having the each location in the connection memory specify an input
channel, multiple outputs can specify the same input address. This can be a
powerful tool used for broadcasting data.
In Processor Mode, the microprocessor writes data to the connection
memory. Each location in the connection memory corresponds to a particular
output stream and channel number and is transferred directly to the parallel-to-
serial converter one time-slot before it is to be output. This data will be output
on the TX streams in every frame until the data is changed by the microprocessor.
As the IDT7290820 can be used in a wide variety of applications, the device
also has memory locations to control the outputs based on operating mode.
Specifically, the IDT7290820 provides five per-channel control bits for the
following functions: processor or connection mode, constant or variable delay,
enables/three-state the TX output drivers and enables/disable the loopback
function. In addition, one of these bits allows the user to control the CCO output.
If an output channel is set to a high-impedance state through the connection
memory, the TX output will be in a high-impedance state for the duration of that
channel. In addition to the per-channel control, all channels on the ST-BUS
®
outputs can be placed in a high impedance state by either pulling the ODE input
pin low or programming the Output Stand-By (OSB) bit in the interface mode
selection register. This action overrides the per-channel programming in the
connection memory bits.
The connection memory data can be accessed via the microprocessor
interface. The addressing of the devices internal registers, data and connection
memories is performed through the address input pins and the Memory Select
(MS) bit of the control register. For details on device addressing, see Software
Control and Control Register bits description (Table 4, 6 and 7).
SERIAL DATA INTERFACE TIMING
The master clock frequency must always be twice the data rate. For serial
data rates of 2.048, 4.096 or 8.192 Mb/s, the master clock (CLK) must be either
at 4.096, 8.192 or 16.384 MHz respectively. The input and output stream data
rates will always be identical.
The IDT7290820 provides two different interface timing modes ST-BUS
®
/
GCI and WFP (wide frame pulse). If the WFPS pin is high, the IDT7290820
is in the wide frame pulse (WFP) frame alignment mode.
In ST-BUS
®
/GCI mode, the input 8 KHz frame pulse can be in either
ST-BUS
®
or GCI format. The IDT7290820 automatically detects the presence
of an input frame pulse and identifies it as either ST-BUS
®
or GCI. In ST-BUS
®
format, every second falling edge of the master clock marks a bit boundary and
the data is clocked in on the rising edge of CLK, three quarters of the way into
the bit cell, see Figure 7. In GCI format, every second rising edge of the master
clock marks the bit boundary and data is clocked in on the falling edge of CLK
at three quarters of the way into the bit cell, see Figure 8.
WIDE FRAME PULSE (WFP) FRAME ALIGNMENT TIMING
When the device is in WFP frame alignment mode, the CLK input must be
at 16.384 MHz, the FE/HCLK input is 4.096 MHz and the 8 KHz frame pulse
is in ST-BUS
®
format. The timing relationship between CLK, HCLK and the frame
pulse is shown in Figure 9.
When WFPS pin is high, the frame alignment evaluation feature is disabled.
However, the frame input offset registers may still be programmed to compensate
for the varying frame delays on the serial input streams.
