LTC3643
7
3643fb
For more information www.linear.com/LTC3643
PIN FUNCTIONS
PGND (Pins 1-2): Ground Pins for the Power Switch.
CAP (Pin 3): Storage Capacitor Connection. This pin is
the power input to the step-down regulator’s main switch
(boost regulator’s synchronous switch) and connects
directly to the backup energy storage capacitor.
V
IN
(Pins 4-5): Input Supply of Boost Charger and Regulated
Output Voltage of Step-Down Regulator. This input also
powers the INTV
CC
LDO and input to the current regula-
tion amplifier.
GATE (Pin 6): Gate Driver for PowerPath Switch. This pin
drives the gate of an external PMOS switch that connects
the main power supply to the system load. This output
swings from V
IN
to GND.
RUN (Pin 7): Logic Controlled RUN Input. Do not leave
this pin floating. Place a resistor divider from V
IN
to GND
for
an accurate V
IN
Undervoltage threshold.
FBSYS (Pin 8): Feedback Input to Step-Down Regulator
Control Loop. Connect a resistor divider tap to this pin. The
V
IN
voltage can be adjusted such that V
IN
= 0.6V (1+R2/R1)
(See Figure 4).
FBCAP (Pin 9): Feedback Input to the Error Amplifier of the
Cap Voltage Regulation Loop. Connect a resistor divider
tap to this pin. The CAP voltage can be
adjusted such that
V
CAP
= 0.6V (1+R4/R3) (See Figure 5).
ITH (Pin 10): Error Amplifier Output and Switching
Regulator Compensation Point for the Boost Regulator.
The current comparator’s trip threshold is linearly
proportional to this voltage. The Buck Regulator’s
compensation is set internally by the part.
CAPGD (Pin 11): Capacitor Good Open Drain Status Output.
This output is pulled down when the LTC3643 is
charging
the storage capacitor. It becomes high impedance when
the output cap reaches 95% of the programmed charge
voltage.
PFO (Pin 12): Power Fail Open Drain Status Output. This
pin pulls down when the main supply voltage is above the
threshold set by the PFI pin.
PFI (Pin 13): Power Fail Input. This pin sets the threshold
at which the converter switches from boost charger mode
to buck regulator
mode. Connect with a resistor divider
from the main power supply in order to switch to buck
regulator mode when the supply voltage drops below a
set threshold.
INTV
CC
(Pin 14): Low Dropout Regulator. Bypass with a
low ESR capacitor of at least 1µF to ground.
BOOST (Pin 15): Boost Rail. Connect a 0.1µF capacitor
between this pin and SW node to power the gate driver
of
the synchronous boost switch.
INDIS (Pins 16-17): Input Disconnect Pin. The Internal
power switch that allows for Output Disconnect feature
is placed between the V
IN
and INDIS pins.
SW (Pins 18-20): Switch Node Connection to the Power
Regulator.
I
LIM
(Pin 21): Buck Mode Peak Current Program Pin.
Leave this pin floating for 3A current limit, ground it for
2A current limit, and tie it to INTV
CC
for 4A current limit
during buck mode.
CLP (Pin 24): Input to Current Regulation Amplifier. This
pin is the inverting input to a current regulation amplifier
that reduces the charging current when CLP rises more
than 50mV above V
IN
.
SGND (Exposed Pad Pin 25): Signal Ground Pin of the
Regulator. Tie to PGND at a single point. Connect to PCB
ground plane for rated thermal performance.
