XRD87L99 xrxr
LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX
REV. 1.0.0
11
FIGURE 7. DNL MEASUREMENT ON PRODUCTION
T
ESTER
The formulas for Differential Non-Linearity (DNL), In-
tegral Non-Linearity (
IN
L) and zero and full scale er-
rors (EZS, EFS) are:
DNL (001) = V002 - V001 - LSB
: : :
DNL (3FE) = V3FF - V3FE - LSB
EFS (full scale error) = V3FF - [V
REF(+)
-1.5 * LSB]
EZS (zero scale error) = V001 - [V
REF(-)
+ 0.5 * LSB]
FIGURE 8. REAL A/D TRANSFER CURVE
Figure 8 shows the zero scale and full scale error
terms.
Figure 9 gives a visual definition of the INL error. The
chart shows a 3-bit converter transfer curve with
greatly exaggerated DNL errors to show the deviation
of the real transfer curve from the ideal one.
After a tester has measured all the transition voltag-
es, the computer draws a line parallel to the ideal
transfer line. By definition the best fit line makes
equal the positive and the negative INL errors. For ex-
ample, an INL error of -1 to +2 LSB's relative to the
Ideal Line would be +
1.5 LSB's relative to the best fit
line.
F
IGURE 9. INL ERROR CALCULATION
1.2 CLOCK AND CONVERSION TIMING
A system will clock the XRD87L99 continuously or it
will give clock pulses intermittently when a conversion
is desired. The timing of Figure 10a shows normal
operation, while the timing of Figure 10b keeps the
XRD87L99 in balance and ready to sample the ana-
log input.
N + 1
N
N - 1
Output
Codes
Analog
Input
(N) Code Width = V
(N+1)
- V
(N)
LSB = [ V
REF(+)
- V
REF(-)
] / 1024
DNL
(N)
= [ V
(N+1)
- V
(N)
] - LSB
LSBDNL
V
(N+1)
V
(N)
DIGITAL
CODES
0.5
∗
LSB
000
001
002
3FE
3FF
V
1.5
∗
LSB
V001 V002 V
3FE
V
3FF
V
REF(-)
V
EZS EFS
7
6
5
4
3
2
1
Output
Codes
Best Fit Line
EFS
EZS
LSB
Real Transfer Line
INL
Analog Input (Volt)
Ideal Transfer Line
