OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

XRD87L99AIQ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
XRD87L99 xrxr
LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX
REV. 1.0.0
13
1.6 DIGITAL INTERFACES
The logic encodes the outputs of the comparators in-
to a binary code and latches the data in a D-type flip-
flop for output.
The functional equivalent of the XRD87L99 (Figure
14) is composed of:
1. Delay stage (t
AP
) from the clock to the sampling
phase (f
S
).
2. An ideal analog switch which samples V
IN
.
3. An ideal A/D which tracks and converts V
IN
with
no delay.
4. A series of two DFF's with specified hold (t
HLD
)
and delay (t
DL
) times.
t
AP
, t
HL
D and t
DL
are specified in the Electrical Charac-
teristics table.
1.7 P
OWER DOWN
Figure 15 shows the relationship between the clock,
sampled V
IN
to output data relationship and the effect
of power down.
F
IGURE 14. XRD87L99 FUNCTIONAL EQUIVALENT
C
IRCUIT AND INTERFACE TIMING
FIGURE 15. POWER DOWN TIMING DIAGRAM
φ
VIN
S
A/D
XRD8799
CLK
DB9-DB0
N N+1
N-1 N
t
DL
t
HLD
D QD Q
DB9-DB0
CLK
VIN
t
AP
N-2 Valid
DB0-DB9
CLK
VIN
PD
IDD, IVREF(+)
SAMPLE
N
SAMPLE
M
SAMPLE
M+1
N-1 Valid N Valid M Valid
t
CLKS1
t
CLKH1
t
PD
t
PU
xrxr XRD87L99
LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX
REV. 1.0.0
14
2.0 APPLICATION NOTES
F
IGURE 16. TYPICAL CIRCUIT CONNECTIONS
The following information will be useful in maximizing
the performance of the XRD87L99.
1. All signals should not exceed AV
DD
+0.5 V or
AGND -0.5 V or DV
DD
+0.5 V or DGND -0.5 V.
2. Any input pin which can see a value outside the
absolute maximum ratings (AV
DD
or DV
DD
+0.5 V
or AGND -0.5 V) should be protected by diode
clamps (HP5082-2835) from input pin to the sup-
plies. All XRD87L99 inputs have input protection
diodes which will protect the device from short
transients outside the supply ranges.
3. The design of a PC board will affect the accuracy
of XRD87L99. Use of wire wrap is not recom-
mended.
4. The analog input signal (V
IN
) is quite sensitive
and should be properly routed and terminated. It
should be shielded from the clock and digital out-
puts so as to minimize cross coupling and noise
pickup.
5. The analog input should be driven by a low
impedance (less than 50
Ω).
6. Analog and digital ground planes should be sub-
stantial and common at one point only. The
ground plane should act as a shield for parasitics
and not a return path for signals. To reduce noise
levels, use separate low impedance ground
paths. DGND should not be shared with other
digital circuitry. If separate low impedance paths
cannot be provided, DGND should be connected
to AGND next to the XRD87L99.
7. DV
DD
should not be shared with other digital cir-
cuitry to avoid conversion errors caused by digital
supply transients. DV
DD
for the XRD87L99 should
be connected to AV
DD
next to the XRD87L99.
8. DV
DD
and AV
DD
are connected inside the
XRD87L99. DGND and AGND are connected
internally.
9. Each power supply and reference voltage pin
should be decoupled with a ceramic (0.1
µF) and
a tantalum (10
µF) capacitor as close to the
device as possible.
10. The digital output should not drive long wires.
The capacitive coupling and reflection will con-
tribute noise to the conversion. When driving dis-
tant loads, buffers should be used. 100
Ω resis-
tors in series with the digital outputs in some
applications reduces the digital output disruption
of A
IN
.
OFW
CLK
DB9 - DB0
OE
AGND DGND
(Substrate)
XRD87L99
AIN1
V
REF(+)
V
REF(-)
3/4 R
1/4 R
Buffer
AV
DD
DV
DD
C1D, C2DC1A, C2A
C1 = 4.7 or 10
µ
F Tantalum
C2 = 0.1
µ
F Chip Cap or low inductance cap
R
T
= Clock Transmission Line Termination
Reference
Voltage
Source
V
REF1(-)
A
IN
C1
C2
C1
C2
C1
C2
+
-
+5 V
R
T
1 of 8
AIN8
Z < 100
Ω
Resistive
Isolation of
50 to 100
Ω
WR
CLK
A2
A1
A0
XRD87L99 xrxr
LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX
REV. 1.0.0
15
FIGURE 17. EXAMPLE OF A REFERENCE VOLTAGE SOURCE
FIGURE 18. ±3V ANALOG INPUT
For R = 5k use Beckman Instruments #694-3-R10k resistor array or equivalent.
NOTE: High R values affect the input BW of ADC due to the (R * C
IN
of ADC) time constant. Therefore, for different applica-
tions the R value needs to be selected as a trade-off between A
IN
settling time and power dissipation.
0.1
µ
F
MP5010
+3V
+
-
+
-
5k
100k
V
REF(+)
V
IN
+
-
R R
A
IN1
V
REF(-)
+3V
+3V +3V
DB0
AGND
AV
DD
1 of 8
A
IN8
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24

XRD87L99AIQ

Mfr. #:
Buy XRD87L99AIQ
Manufacturer:
MaxLinear
Description:
Analog to Digital Converters - ADC LOW POWER 2MSPS 10 BIT 8-CHANNEL
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet