NCN5110
www.onsemi.com
15
C t
ǒ
10s * t
startup,system
Ǔ
I
coupler_lim,startup
VFILTH
The third limit on VFILT capacitor value is the required
capacitor value to filter out current steps DI
step
of the system
without going into reset.
C u
DI
step
2
ǒ
2
ǒ
V
BUS1
* V
coupler_drop
* V
FILTL
Ǔ
I
slope
Ǔ
The last condition on the size of VFILT is the desired
warning time twarning between SAVEB and RESETB in
case the bus voltage drops away. This is determined by the
current consumption of the system Isystem.
C u
I
system
ǒ
t
warning
) t
busfilter
Ǔ
ǒ
V
BUS1
* V
coupler_drop
* V
FILTL
Ǔ
The bus coupler is implemented as a linear voltage
regulator. For efficiency purpose, the voltage drop over the
bus coupler is kept minimal (see Table 4).
KNX Impedance Control
The impedance control circuit defines the impedance of
the bus device during the active and equalization pulses. The
impedance can be divided into a static and a dynamic
component, the latter being a function of time. The static
impedance defines the load for the active pulse current and
the equalization pulse current. The dynamic impedance is
produced by a block, called an equalization pulse generator,
that reduces the device current consumption (i.e. increases
the device impedance) as a function of time during the
equalization phase so as to return energy to the bus.
Fixed and Adjustable DC−DC Converter
The device contains two DC−DC buck converters, both
supplied from VFILT.
DC1 provides a fixed voltage of 3.3 V. This voltage is used
as an internal low voltage supply (V
DDA
and V
DDD
) but can
also be used to power external devices (VDD1−pin). DC1 is
automatically enabled during the power−up procedure (see
Analog State Diagram, p19).
DC2 provides a programmable voltage by means of an
external resistor divider. It is not used as an internal voltage
supply making it not mandatory to use this DC−DC
converter (if not needed, tie the VDD2MV pin to VDD1).
DC2 will only be enabled when the nDC2EN pin is pulled
low. When nDC2EN is pulled to VDDD, the DC2 controller
is disabled.
The voltage divider can be calculated as follows:
R
4
+ R
5
V
DD2
* 1.2
1.2
(eq. 1)
Both DC−DC converters make use of slope control to
improve EMC performance (see Table 5). To operate DC1
and DC2 correctly, the voltage on the VIN−pin should be
higher than the highest value of DC1 and DC2.
Although both DC−DC converters are capable of
delivering 100 mA, the maximum current capability will not
always be usable. One always needs to make sure that the
KNX bus power consumption stays within the KNX
specification. The maximum allowed current for the DC−DC
converters and V20V regulator can be estimated as next:
V
BUS
ǒ
I
BUS
* I
20V
Ǔ
2
ƪ
ǒ
V
DD1
I
DD1
Ǔ
)
ǒ
V
DD2
I
DD2
Ǔ
ƫ
w 1
(eq. 2)
I
BUS
will be limited by the KNX standard and should be
lower or equal to I
coupler
(see Table 4). Minimum V
BUS
is
20 V (see KNX standard). V
DD1
and V
DD2
can be found back
in Table 4. I
DD1
, I
DD2
and I
20V
must be chosen in a correct
way to be in line with the KNX specification (Note 2).
Although DC2 can operate up to 21 V, it will not be
possible to generate this 21 V under all operating conditions.
See application note AND9135 for defining the optimum
inductor and capacitor of the DC−DC converters. When
using low series resistance output capacitors on DC2, it is
advised to split the current sense resistor as shown in
Figure 12 to reduce ripple current for low load conditions.
V20V Regulator
This is the 20 V low drop linear voltage regulator used to
supply external devices. As it draws current from VFILT,
this current is seen without any power conversion directly at
the VBUS1 pin.
The V20V regulator is enabled by pulling the nV20VEN
pin low. When the nV20VEN pin is pulled high, the 20V
regulator is disabled. When the V20V regulator is not used,
no load capacitor needs to be connected (see C7 of Figure 9).
Connect V20V−pin with VFILT−pin in this case.
The 20 V regulator has a current limit that depends on the
FANIN resistor value. In Table 4, the typical value of the
current limit at startup is given as I
20V_lim
.
Xtal Oscillator
An analog oscillator cell generates an optional clock of
16 MHz.
Figure 11. XTAL Oscillator
XTAL1
XTAL2
XCLK
OSC
32
35
34
21
8 MHz @ XCLC = VSS
16 MHz @ XCLC = VDD
VDD
XCLKC
The XCLK−pin can be used to supply a clock signal to the
host controller.
2. The formula is for a typical KNX application. It‘s only given as guidance and does not guarantee compliance with the KNX standard.
