System block diagram description STA2065
10/20 Doc ID 16050 Rev 5
2.6.7 AC97 controller
AC97 audio controller enables SOC to control external AC97 CODECs using SOC AMBA
interconnect. It is implemented in a way to minimize audio data handling by SOC processor
with dedicated audio DMA engine. AC97 Audio Controller supports AC97 revision 2.3
compliant audio CODECs. External interface supports one external AC97 CODEC with 6
output (3 of them can be Double Rate Audio) and 3 input channels.
2.6.8 CAN
STA2065 features one CAN module that is compliant with the CAN specification V2.0 part B
(active). The bit rate can be programmed up to 1 MBaud.
2.7 Specific functions
2.7.1 GPS
STA2065 integrates HPGPS_G2, ST’s proprietary GPS IP, which is ST’s 2nd generation
High-Sensitivity Baseband. The Baseband is fully compliant with GPS and Galileo L1/E1
signal specifications, and is optimized to maximize sensitivity for both acquisition and
tracking in difficult environments. Please refer to GPS solution specifications and software
release notes for more specific performance details.
The baseband accepts a 3-bit signal at a 4MHz IF from its companion RF chip, the
STA5630. It down-converts this to baseband and feeds it to the acquisition engines (for up to
8 satellites simultaneously) and the tracking channels (for up to 32 satellites
simultaneously).
The highly parallel correlators in the acquisition engines identify each satellite signal in time
and frequency domains, and the results are passed to the tracking channels. The tracking
channels fine-tune the lock, then track continuously, providing orbit data and timing
measurements to the ARM CPUs.
The management of the hardware for these operations, and the myriad of complex
conditions that arise, is performed in a complete GPS software library supplied by ST. This
library also takes the resultant measurement data and processes it to maintain satellite
databases and calculate the user's position, velocity and time (PVT) solutions.
The PVT solution, and other useful data, is made available to the user's application via an
API in the ST GPS library. This runs on a royalty-free real-time kernel (OS20), with ports to
industry-standard operating systems also available. In stand-alone mode, the outputs are
generated in standard NMEA message format.
Options are also available in the software library to support ST Self-Trained Assisted GPS
(ST-AGPS), a complete and scalable solution for assisting GPS start-up with Autonomous
Ephemeris prediction when no network is available, and with simple download when a
network is available followed by prediction for the following 7 days.
The GPS subsystem is based on an ARM966 processor and is clocked by two clocks:
● MCLK: ARM966 CPU clock
● RFCLK: 16f0 or 32f0, from RF chip
MCLK is derived from the PLL2 clock with a divisor from 3 to 16, giving an ARM966
operating frequency in the range from 208 to 39 MHz, in the case the PLL2 is running at 624
