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STA2065P2

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
STA2065 System block diagram description
Doc ID 16050 Rev 5 7/20
2.4.2 SD/MMC
STA2065 features two SD/SDIO/MMC interfaces up to 52 MHz / 8-bit. The main clock
available to the peripherals is:
● PLL2CLK/13 (when PLL2CLK is 624 MHz and SRC_MMC52 = 0, 48 MHz will be
generated)
● PLL2CLK/12 (when PLL2CLK is 624 MHz and SRC_MMC = 1, 52 MHz will be
generated)
● PLL2CLK/9 (when PLL2CLK is 432 MHz, 48 MHz will be generated)
The peripheral is compliant to the following standards:
● MMC 4.4
● SD 2.0/Part 1 - Physical Layer
● SD 2.0/Part E1 - SDIO Specification
2.4.3 DDR-SDRAM controller
The SDRAM controller has been designed to support up to 1Gbit over each of the two chip
selects (or up to 2 Gbit over a single chip select) of:
● LP DDR-SDRAM
● DDR2
The memory data bus will be 16 or 32-bit wide for LP DDR-SDRAM memories (under
software control). This same configuration is also supported for DDR2 type of memories.
2.4.4 Smart card interface
STA2065 features a Smart Cart interface compliant to the standard ISO7816-3.
STA2065 supports 3.0 V or 1.8 V type of Cards.
2.5 Audio/video functions
2.5.1 C3
It is composed of CD-ROM Decoder Block, responsible for performing sector de-scrambling
and 3rd level of error correction embedded in the sector specific to CD-ROM mode1 and XA
Form1, and Data Filter block supporting frame data filtering and different block layout
organization possibilities. The C3 block can take its input data directly from SPDIF or from
the memory space, and delivers back its output data to memory, supporting DMA requests.
System block diagram description STA2065
8/20 Doc ID 16050 Rev 5
2.5.2 Sample rate converter (SaRaC)
This block offers a fully digital stereo asynchronous sample rate conversion, using an
automatic Digital Ratio Locked Loop. Its main features are:
● Up to 20-bit input and 22-bit output sample size
● DMA optimized 16-bit stereo sample interface
● Input sample rate from selectable MSP or SPDIF interface (32 kHz to 48 kHz)
● Output sample rate from selectable MSP interface (44.1 kHz to 48 kHz)
● Internally generated input sample rate (8 kHz to 48 kHz) for compressed audio
decoding
2.5.3 JPEG decoder
The JPEG decoder block performs Baseline DCT sequential decoding up to 16Mpix/sec.
JPEG compressed thumbnails are also supported.
2.5.4 Video input
STA2065 has a Video Input Port. The VIP allows to grab images from external devices,
supporting parallel CCIR-656 interface up to 80 MHz.
This block can be used in camera mode with an imaging co-processor or a CVBS video
decoder to store pixel information into system memory. It can be also used in raw mode to
directly store raw data from an external sensor.
2.5.5 Smart graphics accelerator (SGA)
The Smart Graphic Accelerator (SGA) provides an efficient 2D and 3D primitive drawing tool
that breaks down the Mips and power consumption concerns of pixel processing.
2.5.6 Color LCD controller (CLCD)
This interface (18-bit parallel RGB) drives LCD panels. It supports single or dual-panel color
and monochrome STN displays and color TFT or HR-TFT displays. The resolution can be 1,
2 or 4 bit-per-pixel (bpp) palletized for mono STN, 1, 2, 4 or 8 bpp palletized for color STN
and TFT, 16-bpp true-color non palletized for Color STN and TFT, 24-bpp packed or not
packed true color non pallettized for color TFT. It also offers Frame Modulation to deliver
enhanced colors on 12, 16 or 18 bits (HR-) TFT panels from up to 24-bpp format.
STA2065 System block diagram description
Doc ID 16050 Rev 5 9/20
2.6 Communication interfaces
2.6.1 USB
STA2065 embeds one USB2.0 OTG high-speed interface named USB0 featuring:
● High-speed signalling rate at 480 Mbit/s
● Support for full-speed (12 Mbit/s) signaling bit rate
● Support for session request protocol (SRP) and host negotiation protocol (HNP)
● Up to 7 bidirectional endpoints plus control endpoint 0
● 8192 bytes maximum FIFO dimension
● Dynamic FIFO allocation
USB0 is equipped with a built-in USB 2.0 HIGH-SPEED / OTG PHY, while USB1 is
equipped with both an USB 2.0 FULL-SPEED PHY and a standard ULPI interface able to
connect to an external Single Date Rate PHY.
With the goal of reducing the BOM cost for the customer, the USB 2.0 PHY also supports
this additional muxing scheme:
● the USB D- wire is used as either the USB D- signal or UARTn transmit data signal
● the USB D+ wire is used as either the USB D+ signal or the UARTn receive data signal
2.6.2 UART
STA2065 features four Autobaud UARTs. One offers all modem control/status signals. They
are enhanced versions of the industry-standard 16C550 UART.
2.6.3 I
2
C
The I
2
C controller is an interface designed to support the physical and data link layer
according to I
2
C standard revision 2.1 (January 2000). The I
2
C bus is a 2-wire serial bus
that provides a low-cost interconnection between ICs. STA2065 features three I
2
C
interfaces.
2.6.4 MSP
The multichannel serial port (MSP) is a synchronous receive and transmit serial interface.
STA2065 features three MSPs.
2.6.5 SSP
STA2065 features two SSPs up to 24Mbit/sec for synchronous serial communication with
external peripherals. SPI, MicroWire, T.I. and mono-directional protocols are supported with
programmable word length up to 32 bits.
2.6.6 SPDIF
This interface takes SPDIF as input and extracts data and other channel information
encrypted in SPDIF Frame format as per IEC958 standards. Data can be transferred to
memory, using DMA support, or directly to C3 decoder without CPU intervention. SPDIF
block supports up to 2X data streams.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

STA2065P2

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Manufacturer:
STMicroelectronics
Description:
RF Microcontrollers - MCU MID INFOTAINMENT
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