STA2065P2 Datasheet STA2065P2, STA2065N2 | P13-P15

STA2065 System features introduction

Doc ID 16050 Rev 5 13/20

3 System features introduction

In this chapter, an introduction to the main STA2065 system features is given. These will be

explained in detail later in this document.

3.1 Power region partition

STA2065 is a device targeted to a wide range of applications, starting from handheld battery

powered devices thanks to an optimized power management but also addressing in dash

automotive power requirements thanks to its flexible multi-voltage IO.

Three main power regions are identified:

● V

DD_ON

: It is the core voltage that powers the RTC (Real Time Clock), the PMU (Power

Management Unit), SRC (System Clock and Reset controller) and the Backup RAM of

STA2065. V

DD_ON

remains usually powered even when the device is in DEEP-SLEEP

mode. For this reason, the static power consumption of this region stays below 20A

worst case.

● V

: It is the core voltage that powers the overall chip (apart from the IOs). This voltage

is not applied in very low power state condition. When applied, the V

DD_ON

and V

are at the same voltage. A maximum of 10% variation between the two regions is

required.

● V

DDIO

: It is the power region dedicated to the IOs. The overall IOs are divided in seven

groups and each of them can be powered at different, independent voltages. Some

groups may have specific constraints in terms of power voltage range in order to meet

specific electrical characteristics compliant to some standards; some of these groups

are, for example, in the DDR interface and the 1.1 embedded USB transceiver. There is

also a group of IOs called V

DDIO_ON

that identifies the IOs that must be always

powered (also in the lowest power consumption state of STA2065) in order to make the

wake-up possible. The other five regions (called also V

DDIOX

) cannot be powered while

in this state. For more information, please refer to Chapter 3.6: IO groups on page 17

3.2 Frequency region partition

STA2065 is designed so that there are two PLLs. PLL1 generates clock frequencies for the

ARM core and the internal buses, while the PLL2 generates clock frequencies for each

peripheral kernel and also for each peripheral interface. This means that each peripheral

receives the clock derived from the PLL1 at its internal interface, then it works with the clock

derived from the PLL2. Despite the use of two PLLs, a single system clock input or a single

external crystal is needed (in addition to the RTC clock (or crystal)).

System features introduction STA2065

14/20 Doc ID 16050 Rev 5

3.3 Frequency and power range

The core voltage range is 1.25 ±4% V while the IO voltage ranges are 1.8±10% V, 2.5 ±10% V

and 3.3 ±10% V

Tabl e 2 shows some use cases of STA2065 in NORMAL mode:

The background of Tab l e 2 is the maximization of data throughput on the DRAM interface,

matching the currently available DRAM speed grades: 133 MHz, 166 MHz and 200 MHz (LP

DDR) and 333 MHz (DDR2). Regardless of the memory speed grade it is possible to

program the ARM core, the internal bus and the DDR to run at different speeds than the

ones mentioned in Table 2. The ARM bus clock and the bus clock are derived from the same

common source (VCO of the PLL1) but are asynchronous each other. The DDR frequency

can be the same (synchronous) or derived with a different pre-scaling (1, 2, 3, 4, 5, 6, 8, 9 or

10) from the VCO of PLL1 or PLL2 (asynchronous configuration).

STA2065 embeds a complete GPS subsystem where both gate logic and dedicated DSP

work together. There are specific constraints in this subsystem in terms of minimum

frequency in order to guarantee the target GPS specifications.

In the lowest power consumption state possible, only V

DD_ON

is powered and the target

current drawn is 20 A. In this state, the clock is not running and the current leakage is

mainly due to the Backup memory. The 20 A current limit has to be considered with

Process best (leakage worst case condition), V

DD_ON

1.3V (1.25V plus 4% tolerance) and

Junction Temperature 50

C (considering, while in this state, the ambient temperature is

equal to the junction temperature).

Table 2. Frequency and power use cases

and V

dd_on

(V)

Core Freq

[MHz]

Bus Freq

[MHz]

DDR Freq

[MHz]

Sync/Async

[S/A]

1.2 5(±4%) 624 208 312 A, DDR2

1.2 5(±4%) 624 156 156 S

1.2 5(±4%) 624 124.8 124.8 S

1.2 5(±4%) 533 177.67 177.67 S

1.2 5(±4%) 533 133.25 133.25 S

1.2 5(±4%) 533 177.67 312 A, DDR2

1.2 5(±4%) 520 208 130 A

1.2 5(±4%) 520 173.34 173.34 S

1.2 5(±4%) 520 130 130 S

1.2 5(±4%) 520 208 312 A, DDR2

1.2 5(±4%) 494 197.6 197.6 S

1.2 5(±4%) 494 164.67 164.67 S

1.2 5(±4%) 494 123.5 123.5 S

1.2 5(±4%) 494 208 329.34 A, DDR2

STA2065 System features introduction

Doc ID 16050 Rev 5 15/20

3.4 Power states

The following power states are defined:

● OFF: V

DD_ON

and V

are not applied (all data in the backup RAM is lost): no data

retention is kept in the SDRAM

● NORMAL: Each peripheral runs at its nominal speed with the possibility of turning off

all the unused peripherals (peripheral kernel clock gated)

● SLOW: PLL1 bypassed. ARM and bus runs at crystal clock. PLL2 runs at its nominal

speed. PLL1 can be optionally put in power down

● DOZE: It is like SLOW mode with the ARM running either at 19 MHz or 32 KHz

● STANDBY: This power mode is achieved through software configuration of the Normal

mode. PLLs run at their nominal speed. ARM1176 is in WFI (Wait For Interrupt) state

and its clock is automatically gated off.

● DEEP-SLEEP: V

powered off. V

DD_ON

powered (RTC, few GPIOs, backup RAM)

and clocked at 32 KHz making the wakeup possible. The context is put, optionally, in

the external SDRAM if they are in self refresh mode. Only the V

and V

DDIO_ON

regions must be powered

● SLEEP: It is like the DEEP-SLEEP mode, with the difference that V

and V

DDIO

are

also applied and the PLLs are off (optional for PLL2)

While in NORMAL, SLOW AND STANDBY, V

DD_ON

and V

are the same (10% tolerance

between them) and cannot be changed. Also the power to the several IO groups is kept

unchanged.

In order to change the V

DD_ON

and V

values, the system has to transit to either OFF,

SLEEP, DEEP-SLEEP and then back to the selected state.

In order to keep the power consumption as low as possible, the target voltage mentioned in

DEEP-SLEEP is considered at 1.0V.

A dedicated FSM manages the power state transitions among NORMAL, SLOW, DOZE

AND SLEEP. All other states mentioned above are SW variants of the ones managed by the

FSM.

Tabl e 3 shows the summary of the power states supported by STA2065.

Table 3. Power mode states

Power State 32kHz PLL1 PLL2 V

DD_ON

IOs

OFF off off off off off off

NORMAL on on on = V

1.2V to 1.3V

(1.25V typ)

1.7 to 3.6V

SLOW on

Off. Bypassed

by main

oscillator

off (SW can take

it on)

= V

1.2V to 1.3V

(1.25V typ)

1.7 to 3.6V

DOZE on

Off. Bypassed

by 32 kHz

off (SW can take

it on)

= V

1.2V to 1.3V

(1.25V typ)

1.7 to 3.6V

STANDBY on

on (clk gated)

ARM in WFI

on (clk gated) = V

1.2V to 1.3V

(1.25V typ)

1.7 to 3.6V

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21

STA2065P2

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