ADP5587 Data Sheet
Rev. D | Page 12 of 24
GENERAL-PURPOSE INPUTS AND OUTPUTS
The ADP5587 supports up to 18 programmable GPIOs that can
be configured to address a variety of uses. Figure 14 shows the
makeup of a typical GPIO block where GPIOx represents any of
the 18 I/O lines.
DEBOUNCE
GPIOx
Dx_DIR
Dx_OUT
Dx_IN
Dx_IN_DBNC
Dx_PULL
V
CC
V
CC
08612-010
NOTES:
1. Dx_IN STANDS FOR ANY OF THE 18 GPIOs CONFIGURED AS GPIs.
2. Dx_OUT STANDS FOR ANY OF THE 18 GPIOs CONFIGURED AS GPOs.
3. Dx_IN_DBNC STANDS FOR GPI DEBOUNCE.
4. Dx_DIR STANDS FOR GPIO DIRECTION.
5. Dx_PULL STANDS FOR GPIO PULL-UP.
Figure 14. Typical GPIO Block
General-Purpose Inputs (GPI)
The ADP5587 allows the user to configure all or some of its
GPIOs as general-purpose inputs (GPIs). After the GPIOs are
configured as GPIs, the user can choose to also turn on pull-up
resistors and interrupt generation capability, thus reducing the
amount of software monitoring and processor interaction and
saving power.
The programmed level of the GPI interrupt determines the
active level of the GPI pin. For example, if a GPI interrupt level
is programmed as high, a high on that pin is considered active
and meets the interrupt requirement. If the interrupt is pro-
grammed as low, a low on that pin is considered active and
meets the interrupt requirement.
GPI data status and interrupt status are reflected in the GPIO
interrupt status and data status registers (Register 0x11 through
Register 0x16). Caution is necessary during software imple-
mentation because an interrupt may be set immediately after
the registers are s et. To prevent this, the correct logic levels
must be present at the GPIs, and the GPIO interrupt level must
be set before GPIO interrupt enable or GPI event FIFO enable
registers are set. Figure 15 shows the interrupt generation
scheme, where Dx represents any one of the 18 GPIOs.
Dx_IN
Dx_IN_IEN
REG. 0x23
THROUGH
REG. 0x25
Dx_IN_ISTAT
REG. 0x11
THROUGH
REG. 0x13
READ TWICE
TO CLEAR
GPI_INT
REG. 0x02
WRITE 1
TO CLEAR
REG. 0x01
INT
DRIVE
INTERRUPT
CONDITION
DECODE
Dx_ILVL
REG. 0x26
THROUGH
REG. 0x28
AND
08612-011
NOTES:
1. Dx_IN STANDS FOR ANY OF THE 18 GPIOs CONFIGURED AS GPIs.
2. Dx_ILVL STANDS FOR GPIO INTERRUPT LEVEL.
3. Dx_IN_IEN STANDS FOR GPI INTERRUPT ENABLE.
4. Dx_IN_STAT STANDS FOR GPI INTERRUPT STATUS.
5. GPI_INT STANDS FOR GPI INTERRUPT.
Figure 15. GPIO Interrupt Generation
GPI Events
A column or row configured as a GPI can be programmed to be
part of the key event table and is, therefore, also capable of
generating a key event interrupt. A key event interrupt caused
by a GPI follows the same process flow as a key event interrupt
caused by a key press or key release. GPIs configured as part of
the key event table allow single key switches and other GPI
interrupts to be monitored. As part of the event table, GPIs are
represented by a decimal value of 97 (0x61 hexadecimal or
1100001 binary) through a decimal value of 114 (0x72
hexadecimal or 1110010 binary). See Table 12 and Table 13 for
GPI event number assignments for rows and columns,
respectively.
Table 12. GPI Event Number Assignments for Rows
R0 R1 R2 R3 R4 R5 R6 R7
97 98 99 100 101 102 103 104
Table 13. GPI Event Number Assignments for Columns
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
105 106 107 108 109 110 111 112 113 114
For a GPI that is set as active high and is enabled in the key
event table, the state machine adds an event to the event count
and event tables whenever that GPI goes high. If the GPI is set
to active low, a transition from high to low is considered a press
and is also added to the event count and event table. After the
interrupt state is met, the state machine internally sets an
interrupt for the opposite state programmed in the register to
prevent polling for the released state, thereby saving current.
After the released state is achieved, it is added to the event table.
The press and release are still indicated by Bit 7 in the event
register (Register 0x04 through Register 0x0D). The GPI events
can also be used as unlocked sequences.
When the GPI_EM_REGx bit in Register 0x20 through Register
0x22 is set, GPI events are not tracked when the keypad is locked.
The GPIEM_CFG bit (Register 0x01, Bit 6) must be cleared for
the GPI events to be tracked in the event counter and event
table when the keypad is locked.
Data Sheet ADP5587
Rev. D | Page 13 of 24
275 Microsecond Interrupt Configuration
The ADP5587 gives the user the flexibility of deasserting the
interrupt for 275 μs while there is a pending event. When the
INT_CFG bit in Register 0x01 is set, any attempt to clear the
interrupt bit while the interrupt pin is already asserted results
in a 275 μs deassertion. When the INT_CFG bit is cleared, the
processor interrupt remains asserted if the host tries to clear
the interrupt. This feature is particularly useful for software
development and edge triggering applications.
Debouncing
The ADP5587 has a 275 μs debounce time for GPIOs configured
as GPIs and rows in keypad scanning mode. The reset line
always has a 275 μs debounce time.
General-Purpose Outputs (GPOs)
The ADP5587 allows the user to configure all or some of its
GPIOs as GPOs. These GPOs can be used as extra enables for
the host processor or simply as trigger outputs. When configured
as an output (GPO), a digital buffer drives the pin to 0 V for a 0
and to V
CC
for a 1. To se t any GPIO as a GPO, make sure that
the corresponding bits in Register 0x1D through Register 0x1F are
set for GPIO mode; then use Register 0x23 through Register 0x25
to set the corresponding bits for GPO mode.
Power-On Reset
For built-in power-up initialization for applications lacking a
power-on reset signal, a reset pin,
RST
, allows the user to reset
the registers to default values in the event of a brownout or
other reset condition.
Table 14. Device Configuration
Keypad GPIO
Matrix Active Pins Number of Keys Available GPIO Number of GPIOs
10 × 8 C0 to C9, R0 to R7 80 0 0
8 × 8 C0 to C7, R0 to R7 64 C8, C9 2
8 × 7
C0 to C7, R0 to R6
56
R7, C8, C9
3
8 × 6 C0 to C7, R0 to R5 48 R6, R7, C8, C9 4
8 × 5 C0 to C7, R0 to R4 40 R5 to R7, C8, C9 5
7 × 7 C0 to C6, R0 to R6 49 R7, C7 to C9 4
7 × 6 C0 to C6, R0 to R5 42 R6, R7, C7 to C9 5
7 × 5 C0 to C6, R0 to R4 35 R5 to R7, C7 to C9 6
6 × 6 C0 to C5, R0 to R5 36 R6, R7, C6 to C9 6
6 × 5 C0 to C5, R0 to R4 30 R5 to R7, C6 to C9 7
6 × 4 C0 to C5, R0 to R3 24 R4 to R7, C6 to C9 8
0 × 0 None 0 R0 to R7, C0 to C9 18
ADP5587 Data Sheet
Rev. D | Page 14 of 24
I
2
C PROGRAMMING AND DIGITAL CONTROL
The ADP5587 provides full I
2
C software programmability to
facilitate its adoption in various product architectures. All
register programming is done via the I
2
C bus. The LFCSP
package has two options for I
2
C addressing.
The default part option I
2
C write address is located at 0x68
(0b01101000), and the read address is at 0x69 (0b 01101001).
The ADP5587ACPZ-1-R7 has the I
2
C write address at 0x60 (0b
01100000) and the read address at 0x61 (0b 01100001).
All communication to the ADP5587 is performed via its I
2
C-
compatible serial interface. Figure 16 shows a typical write
sequence for programming an internal register. The cycle
begins with a start condition followed by the chip write address.
The ADP5587 acknowledges the chip write address byte by
pulling the data line low. The address of the register to which
data is to be written is sent next. The ADP5587 acknowledges
the register address byte by pulling the data line low. The data
byte to be written is sent next. The ADP5587 acknowledges the
data byte by pulling the data line low, and a stop condition
completes the sequence.
Figure 17 shows a typical read sequence for reading back an
internal register. The cycle begins with a start condition
followed by the chip write address. The ADP5587 acknowledges
the chip write address byte by pulling the data line low. The
address of the register from which data is to be read is sent next.
The ADP5587 acknowledges the register address byte by pulling
the data line low. The cycle continues with a repeat start
followed by the chip read address. The ADP5587 acknowledges
the chip read address byte by pulling the data line low. The
ADP5587 places the contents of the previously addressed
register on the bus for readback. There is no acknowledge
following the readback data byte, and a stop condition
completes the cycle.
SUBADDRESS
CHIP ADDRESS
1
ST 0 1 1 0 1 0 0 0 0 0 SP
0 = WRITE
ADP5587 ACK
ADP5587 ACK
ADP5587 RECEIVES D ATA
ADP5587 ACK
0
08612-012
1
DEFAULT WRITEADDRESS IS 0x68. OPTION 1 WRITE ADDRESS IS 0x60.
Figure 16. I
2
C Write Sequence
SUBADDRESSCHIP ADDRESS
1
CHIP ADDRESS
2
ST 0 1 1 0 1 0 0 0 0 0 0 0 0 0 1 1 0 ST 0 1 1 0 1 0 0 0 1 SP
1 = READ
ADP5587 NO ACK
ADP5587 SENDS DATA
ADP5587 ACK
ADP5587 ACK
ADP5587 ACK
0 = WRITE
0 1
08612-013
1
DEFAULT WRITEADDRESS IS 0x68. OPTION 1 WRITE ADDRESS IS 0x60.
2
DEFAULT READ ADDRESS IS 0x69. OPTION 1 READ ADDRESS IS 0x61.
Figure 17. I
2
C Read and Write Sequences
READ START ADDR
CHIP ADDRESS CHIP ADDRESS
1
ST 0 1 1 0 1 0 0 0 0 0 0 0 0 0 1 1 0 ST 0 1 1 0 1 0 0 0 0
1 = READ
ADP5587 ACK
ADP5587 SENDS DATA 1
ADP5587 ACK
ADP5587 ACK
ADP5587 ACK
0 = WRITE
0 1
ADP5587 NO ACK
1
ADP5587 SENDS DATA N
...
ST
STOP
START
08612-014
1
DEFAULT READ ADDRESS IS 0x69. OPTION 1 READ ADDRESS IS 0x61.
Figure 18. I
2
C Read Auto-Increment

ADP5587ACBZ-R7

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Interface - I/O Expanders QWERTY Keypad Cntlr
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet