CS48DV2B Data Sheet
32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby
DS875F2 Copyright 2009 Cirrus Logic 13
CONFIDENTIAL
CONFIDENTI
A
L
DRA
FT
DELP
HI
5.8 Switching Characteristics — Internal Clock
Parameter Symbol Min Max Unit
Internal DCLK frequency
1
CS48DV2B-CQZ
CS48DV2B-DQZ
1. After initial power-on reset, F
dclk
= F
xtal
. After initial kickstart commands, the PLL is locked to max F
dclk
and remains locked until
the next power-on reset.
F
dclk
-
F
xtal
F
xtal
150
150
MHz
Internal DCLK period
1
CS48DV2B-CQZ
CS48DV2B-DQZ
DCLKP -
6.7
6.7
1/F
xtal
1/F
xtal
ns
CS48DV2B Data Sheet
32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby
14 Copyright 2009 Cirrus Logic DS875F2
CONFIDENTIAL
CONFIDENTI
A
L
DRA
FT
D
ELPHI
5.9 Switching Characteristics — Serial Control Port - SPI Slave Mode.
Figure 3. Serial Control Port - SPI Slave Mode Timing
Parameter Symbol Min Typical Max Units
SCP_CLK frequency
1
1. The specification f
spisck
indicates the maximum speed of the hardware. The system designer should be aware that the actual
maximum speed of the communication port may be limited by the firmware application. Flow control using the SCP_BSY
pin
should be implemented to prevent overflow of the input data buffer. At boot the maximum speed is F
xtal
/3.
f
spisck
-25MHz
SCP_CS
falling to SCP_CLK rising t
spicss
24 - ns
SCP_CLK low time t
spickl
20 - ns
SCP_CLK high time t
spickh
20 - ns
Setup time SCP_MOSI input t
spidsu
5-ns
Hold time SCP_MOSI input t
spidh
5-ns
SCP_CLK low to SCP_MISO output valid t
spidov
-11ns
SCP_CLK falling to SCP_
IRQ rising t
spiirqh
-20ns
SCP_CS
rising to SCP_IRQ falling t
spiirql
0ns
SCP_CLK low to SCP_CS
rising t
spicsh
24 - ns
SCP_CS
rising to SCP_MISO output high-Z t
spicsdz
-20 ns
SCP_CLK rising to SCP_BSY
falling t
spicbsyl
-3
*
DCLKP+20 ns
SCP_BSY
SCP_CS
SCP_CLK
S
CP_MOSI
S
CP_MISO
SCP_IRQ
0
12670
56
7
t
spicss
t
spickl
t
spickh
t
spidsu
t
spidh
t
spidov
A6 A5 A0 R/W MSB LSB
MSB
LSB
t
spicsh
t
spibsyl
t
spiirql
t
spiirqh
f
spisck
t
spicsdz
CS48DV2B Data Sheet
32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby
DS875F2 Copyright 2009 Cirrus Logic 15
CONFIDENTIAL
CONFIDENTI
A
L
DRA
FT
DELP
HI
5.10 Switching Characteristics — Serial Control Port - SPI Master Mode
Figure 4. Serial Control Port - SPI Master Mode Timing
Parameter Symbol Min Typical Max Units
SCP_CLK frequency
1
1. The specification f
spisck
indicates the maximum speed of the hardware. The system designer should be aware that the actual
maximum speed of the communication port may be limited by the firmware application.
f
spisck
-F
xtal
/2
2
2. See Section 5.7.
MHz
SCP_CS
falling to SCP_CLK rising
3
3. SCP_CLK PERIOD refers to the period of SCP_CLK as being used in a given application. It does not refer to a tested parameter
t
spicss
- 11*DCLKP +
(SCP_CLK PERIOD)/2
-ns
SCP_CLK low time t
spickl
20 - ns
SCP_CLK high time t
spickh
20 - ns
Setup time SCP_MISO input t
spidsu
9-ns
Hold time SCP_MISO input t
spidh
5-ns
SCP_CLK low to SCP_MOSI output valid t
spidov
-8ns
SCP_CLK low to SCP_
CS falling t
spicsl
7-ns
SCP_CLK low to SCP_CS
rising t
spicsh
- 11*DCLKP +
(SCP_CLK PERIOD)/2
-ns
Bus free time between active SCP_CS t
spicsx
3*DCLKP - ns
SCP_CLK falling to SCP_MOSI output high-Z t
spidz
-20ns
EE_CS#
SCP_CLK
S
CP_MISO
S
CP_MOSI
0
12670
56
7
t
spicss
t
spickl
t
spickh
t
spidsu
t
spidh
t
spidov
A6 A5 A0 R/W MSB LSB
MSB
LSB
t
spicsh
t
spicsx
f
spisck
t
spidz
t
spicsl

CS48DV2B-CQZR

Mfr. #:
Manufacturer:
Cirrus Logic
Description:
Audio DSPs I/C 12 Ch Audio Enhancement Processr
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet