CS48DV2B Data Sheet
32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby
16 Copyright 2009 Cirrus Logic DS875F2
CONFIDENTIAL
CONFIDENTI
A
L
DRA
FT
D
ELPHI
5.11 Switching Characteristics — Serial Control Port - I
2
C Slave Mode
Figure 5. Serial Control Port - I
2
C Slave Mode Timing
Parameter Symbol Min Typical Max Units
SCP_CLK frequency
1
1. The specification f
iicck
indicates the maximum speed of the hardware. The system designer should be aware that the actual
maximum speed of the communication port may be limited by the firmware application. Flow control using the SCP_BSY
pin
should be implemented to prevent overflow of the input data buffer.
f
iicck
- 400 kHz
SCP_CLK low time t
iicckl
1.25 - µs
SCP_CLK high time t
iicckh
1.25 - µs
SCP_CLK rising to SCP_SDA rising or falling for
START or STOP condition
t
iicckcmd
1.25 µs
START condition to SCP_CLK falling t
iicstscl
1.25 - µs
SCP_CLK falling to STOP condition t
iicstp
2.5 - µs
Bus free time between STOP and START conditions t
iicbft
3-µs
Setup time SCP_SDA input valid to SCP_CLK rising t
iicsu
100 ns
Hold time SCP_SDA input after SCP_CLK falling t
iich
20 - ns
SCP_CLK low to SCP_SDA out valid t
iicdov
-18ns
SCP_CLK falling to SCP_IRQ
rising t
iicirqh
-3
*
DCLKP + 40 ns
NAK condition to SCP_IRQ
low t
iicirql
3
*
DCLKP + 20 ns
SCP_CLK rising to SCB_BSY
low t
iicbsyl
-3
*
DCLKP + 20 ns
S
CP_BSY
S
CP_CLK
SCP_SDA
SCP_IRQ
01 67801 7
t
iicckl
t
iicckh
t
iicsu
t
iich
A6 A0 R/W ACK
LSB
t
iicirqh
t
iicirql
8
ACK
MSB
t
iicstp
6
t
iiccbsyl
t
iicdov
t
iicb
ft
t
iicstscl
t
iicckcmd
f
iicck
t
iicckcmd
t
iicf
t
iicr
CS48DV2B Data Sheet
32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby
DS875F2 Copyright 2009 Cirrus Logic 17
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CONFIDENTI
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DELP
HI
5.12 Switching Characteristics — Serial Control Port - I
2
C Master Mode
Figure 6. Serial Control Port - I
2
C Master Mode Timing
Parameter Symbol Min Max Units
SCP_CLK frequency
1
1. The specification f
iicck
indicates the maximum speed of the hardware. The system designer should be aware that the actual
maximum speed of the communication port may be limited by the firmware application.
f
iicck
-400kHz
SCP_CLK low time t
iicckl
1.25 - µs
SCP_CLK high time t
iicckh
1.25 - µs
SCP_SCK rising to SCP_SDA rising or falling for START or
STOP condition
t
iicckcmd
1.25 µs
START condition to SCP_CLK falling t
iicstscl
1.25 - µs
SCP_CLK falling to STOP condition t
iicstp
2.5 - µs
Bus free time between STOP and START conditions t
iicbft
3-µs
Setup time SCP_SDA input valid to SCP_CLK rising t
iicsu
100 ns
Hold time SCP_SDA input after SCP_CLK falling t
iich
20 - ns
SCP_CLK low to SCP_SDA out valid t
iicdov
-18ns
S
CP_CLK
S
CP_SDA
01 67801 7
t
iicckl
t
iicckh
t
iicsu
t
iich
A6 A0 R/W ACK
LSB
8
ACK
MSB
t
iicstp
6
t
iicdov
t
iic
bf
t
iicstscl
t
iicckcmd
f
iicck
t
iicckcmd
t
iicf
t
iicr
CS48DV2B Data Sheet
32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby
18 Copyright 2009 Cirrus Logic DS875F2
CONFIDENTIAL
CONFIDENTI
A
L
DRA
FT
D
ELPHI
5.13 Switching Characteristics — Digital Audio Slave Input Port
Figure 7. Digital Audio Input (DAI) Port Timing Diagram
5.14 Switching Characteristics — DSD Slave Input Port
Figure 8. Direct Stream Digital - Serial Audio Input Timing
Parameter Symbol Min Max Unit
DAI_SCLK period T
daiclkp
40 - ns
DAI_SCLK duty cycle - 45 55 %
Setup time DAI_DATAn t
daidsu
10 - ns
Hold time DAI_DATAn t
daidh
5-ns
Parameter Symbol Min Typ Max Unit
DSD_SCLK Pulse Width Low t
sclkl
78 - - ns
DSD_SCLK Pulse Width High t
sclkh
78 - - ns
DSD_SCLK Frequency (64x Oversampled) - 1.024 - 3.2 MHz
DSD_A / _B valid to DSD_SCLK rising setup time t
sdlrs
20 - - ns
DSD_SCLK rising to DSD_A or DSD_B hold time t
sdh
20 - - ns
DAI_SCLK
D
AI_DATAn
t
daidh
t
daidsu

CS48DV2B-CQZR

Mfr. #:
Manufacturer:
Cirrus Logic
Description:
Audio DSPs I/C 12 Ch Audio Enhancement Processr
Lifecycle:
New from this manufacturer.
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