© Semiconductor Components Industries, LLC, 2015
October, 2015 − Rev. 3
1 Publication Order Number:
NBA3N200S/D
NBA3N200S
3.3 V Automotive Grade
M-LVDS Driver Receiver
Description
The NBA3N200S is a 3.3 V supply differential Multipoint Low
Voltage (M−LVDS) line Driver and Receiver for automotive
applications. NBA3N200S offers the Type−1 receiver threshold at
0.0 V.
The NBA3N200S has Type−1 receivers that detect the bus state with
as little as 50 mV of differential input voltage over a common−mode
voltage range of −1 V to 3.4 V. Type−1 receivers have near zero
thresholds (±50 mV) and exhibit 25 mV of differential input voltage
hysteresis to prevent output oscillations with slowly changing signals
or loss of input.
NBA3N200S supports Simplex or Half Duplex bus configurations.
Features
Low−Voltage Differential 30 W to 55 W Line Drivers and Receivers
for Signaling Rates Up to 200 Mbps
Type−1 Receivers Incorporate 25 mV of Hysteresis
Controlled Driver Output Voltage Transition Times for Improved
Signal Quality
−1 V to 3.4 V Common−Mode Voltage Range Allows Data Transfer
With up to 2 V of Ground Noise
Bus Pins High Impedance When Disabled or VCC 1.5 V
M−LVDS Bus Power Up/Down Glitch Free
Operating range: VCC = 3.3 ±10% V( 3.0 to 3.6 V)
Operation from –40°C to 125°C
AEC−Q100 Qualified and PPAP Capable
These are Pb−Free Devices
Applications
Low−Power High−Speed Short−Reach Alternative to TIA/EIA−485
Backplane or Cabled Multipoint Data and Clock Transmission
Cellular Base Stations
Central−Office Switches
Network Switches and Routers
Automotive
MARKING
DIAGRAMS
www.onsemi.com
See detailed ordering and shipping information on page 18 o
f
this data sheet.
ORDERING INFORMATION
SOIC−8
D SUFFIX
CASE 751
1
8
NA200
AYWW
G
1
8
NA200 = Specific Device Code
A = Assembly Location
Y = Year
WW = Work Week
G = Pb−Free Package
NBA3N200S
www.onsemi.com
2
Figure 1. Logic Diagram
B
GND
V
CC
DE A
RE
D
R
1
2
3
4
8
7
6
5
SOIC−8
Figure 2. Pinout Diagram
(Top View)
Table 1. PIN DESCRIPTION
Number Name I/O Type Open Default Description
1 R LVCMOS Output Receiver Output Pin
2 RE LVCMOS Input High Receiver Enable Input Pin (LOW = Active, HIGH = High Z
Output)
3 DE LVCMOS Input Low Driver Enable Input Pin (LOW = High Z Output, HIGH=Active)
4 D LVCMOS Input Driver Input Pin
5 GND Ground Supply pin. Pin must be connected to power supply to
guarantee proper operation.
6 A M−LVDS Input
/Output
Transceiver True Input/Output Pin
7 B M−LVDS Input
/Output
Transceiver Invert Input/Output Pin
8 VCC Power Supply pin. Pin must be connected to power supply to
guarantee proper operation.
NBA3N200S
www.onsemi.com
3
Table 2. DEVICE FUNCTION TABLE
TYPE 1 Receiver
Inputs Output
V
ID
= V
A
− V
B
RE R
V
ID
w 50 mV L H
−50 mV < V
ID
< 50 mV L ?
V
ID
−50 mV L L
X H Z
X Open Z
Open L ?
DRIVER
Input Enable Output
D DE A / Y B / Z
L H L H
H H H L
Open H L H
X Open Z Z
X L Z Z
H = High, L = Low, Z = High Impedance, X = Don’t Care, ? = Indeterminate

NBA3N200SDG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Clock Drivers & Distribution MLVDS DRIVER RECEIVER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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